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From: "Björn Töpel" <bjorn@kernel.org>
To: Andy Chiu <andy.chiu@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alexghiti@rivosinc.com>,
	Zong Li <zong.li@sifive.com>,
	Steven Rostedt <rostedt@goodmis.org>,
	Masami Hiramatsu <mhiramat@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Nathan Chancellor <nathan@kernel.org>,
	Nick Desaulniers <ndesaulniers@google.com>,
	Bill Wendling <morbo@google.com>,
	Justin Stitt <justinstitt@google.com>,
	Puranjay Mohan <puranjay@kernel.org>
Cc: Palmer Dabbelt <palmer@rivosinc.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-trace-kernel@vger.kernel.org, llvm@lists.linux.dev,
	Andy Chiu <andy.chiu@sifive.com>
Subject: Re: [PATCH v2 3/6] riscv: ftrace: prepare ftrace for atomic code patching
Date: Wed, 14 Aug 2024 14:57:52 +0200	[thread overview]
Message-ID: <87sev78dnz.fsf@all.your.base.are.belong.to.us> (raw)
In-Reply-To: <87wmkk8toq.fsf@all.your.base.are.belong.to.us>

Björn Töpel <bjorn@kernel.org> writes:

> Andy Chiu <andy.chiu@sifive.com> writes:
>
>> We use an AUIPC+JALR pair to jump into a ftrace trampoline. Since
>> instruction fetch can break down to 4 byte at a time, it is impossible
>> to update two instructions without a race. In order to mitigate it, we
>> initialize the patchable entry to AUIPC + NOP4. Then, the run-time code
>> patching can change NOP4 to JALR to eable/disable ftrcae from a
>                                       enable        ftrace
>
>> function. This limits the reach of each ftrace entry to +-2KB displacing
>> from ftrace_caller.
>>
>> Starting from the trampoline, we add a level of indirection for it to
>> reach ftrace caller target. Now, it loads the target address from a
>> memory location, then perform the jump. This enable the kernel to update
>> the target atomically.
>
> The +-2K limit is for direct calls, right?
>
> ...and this I would say breaks DIRECT_CALLS (which should be implemented
> using call_ops later)?

Thinking a bit more, and re-reading the series.

This series is good work, and it's a big improvement for DYNAMIC_FTRACE,
but

+int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
+{
+	unsigned long distance, orig_addr;
+
+	orig_addr = (unsigned long)&ftrace_caller;
+	distance = addr > orig_addr ? addr - orig_addr : orig_addr - addr;
+	if (distance > JALR_RANGE)
+		return -EINVAL;
+
+	return __ftrace_modify_call(rec->ip, addr, false);
+}
+

breaks WITH_DIRECT_CALLS. The direct trampoline will *never* be within
the JALR_RANGE.

Unless we're happy with a break (I'm not) -- I really think Puranjay's
CALL_OPS patch needs to be baked in in the series!


Björn

  reply	other threads:[~2024-08-14 12:57 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-28 11:47 [PATCH v2 0/6] riscv: ftrace: atmoic patching and preempt improvements Andy Chiu
2024-06-28 11:47 ` [PATCH v2 1/6] riscv: ftrace: support fastcc in Clang for WITH_ARGS Andy Chiu
2024-08-13 11:09   ` Björn Töpel
2024-08-22  8:39     ` Andy Chiu
2024-06-28 11:47 ` [PATCH v2 2/6] riscv: ftrace: align patchable functions to 4 Byte boundary Andy Chiu
2024-08-13 11:11   ` Björn Töpel
2024-06-28 11:47 ` [PATCH v2 3/6] riscv: ftrace: prepare ftrace for atomic code patching Andy Chiu
2024-08-13 12:59   ` Björn Töpel
2024-08-14 12:57     ` Björn Töpel [this message]
2024-09-11 10:57       ` Andy Chiu
2024-09-11 14:37         ` Björn Töpel
2024-09-11 15:03           ` Tao Chiu
2024-09-11 17:16             ` Björn Töpel
2024-06-28 11:47 ` [PATCH v2 4/6] riscv: ftrace: do not use stop_machine to update code Andy Chiu
2024-06-28 11:47 ` [PATCH v2 5/6] riscv: vector: Support calling schedule() for preemptible Vector Andy Chiu
2024-06-28 11:47 ` [PATCH v2 6/6] riscv: ftrace: support PREEMPT Andy Chiu
2024-08-13 11:00 ` [PATCH v2 0/6] riscv: ftrace: atmoic patching and preempt improvements Björn Töpel

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