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From:   =?utf-8?B?QmrDtnJuIFTDtnBlbA==?= <bjorn@kernel.org>
To:     Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        linux-riscv@lists.infradead.org
Cc:     =?utf-8?B?QmrDtnJuIFTDtnBlbA==?= <bjorn@rivosinc.com>,
        linux-kernel@vger.kernel.org, linux@rivosinc.com,
        Palmer Dabbelt <palmer@rivosinc.com>,
        =?utf-8?Q?R?= =?utf-8?Q?=C3=A9mi?= Denis-Courmont 
        <remi@remlab.net>, Darius Rad <darius@bluespec.com>,
        Andy Chiu <andy.chiu@sifive.com>
Subject: Re: [PATCH v2] riscv: Discard vector state on syscalls
In-Reply-To: <87y1k6m827.fsf@all.your.base.are.belong.to.us>
References: <20230626165736.65927-1-bjorn@kernel.org>
 <87y1k6m827.fsf@all.your.base.are.belong.to.us>
Date:   Mon, 26 Jun 2023 20:04:13 +0200
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Bj=C3=B6rn T=C3=B6pel <bjorn@kernel.org> writes:

> Bj=C3=B6rn T=C3=B6pel <bjorn@kernel.org> writes:
>
>> From: Bj=C3=B6rn T=C3=B6pel <bjorn@rivosinc.com>
>>
>> The RISC-V vector specification states:
>>   Executing a system call causes all caller-saved vector registers
>>   (v0-v31, vl, vtype) and vstart to become unspecified.
>
> A bit of a corner case, but this will make sigreturn syscalls discard
> the vector state as well.
>
> Is that an issue? E.g. a user cannot build userspace context switching
> application. Does arm64 SVE handle sigreturn in a special way?

NVM; My bad. The vector state is cleared on *entry*, but then the
registers passed on signal stack is restored as usual.

Sorry for the noise! We're all good!
Bj=C3=B6rn