From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAE624B3365 for ; Fri, 4 Sep 2026 14:17:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788531457; cv=none; b=ky0Ea03HBntxw+kU80XtTW/BjVoxVGHpyUIWYEXozEIUC1j2phQpR/nN3uviyBJ14ebtOem8DjWsJjMzIJyM0aEgL3hN6JTGQWQGB0T+zr3x5f76d9lBB+CmOWeq7MIOBSDmO/AX0FIY/yp9L5X0Ls4rgvwfr+7ONAsCKmcwYC0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788531457; c=relaxed/simple; bh=HKlCbSvo0dNLlf3v1BheuLBrraIIimPq4/G3TaHUcXI=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=lMAO72NFFOv8bRy5tADrCjp20ZMYAWSXw0KByVg0NivM9HBAxPMxzXDxHD87UjhO5wRlzzTg9mNGTICpUnHdUmRBcASt0DoD9N9elpIl7j5EmLaGHQA9YSjlqTP639ro6K4patfK3es3gbU6vBqaocxFtAqAO5O4lmyp8szX5DI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hSkLPCUQ; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hSkLPCUQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 578221F00A3D; Fri, 4 Sep 2026 14:17:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788531455; bh=20zlPSRECV/prMcBjc8mTQlsecPP4fstkjGI7hAkh0g=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=hSkLPCUQH9h2xP4hiF5/50OgzXwXoDZRi92LExr9GuGCvoulWH/u5lL4UKHKyQmoN T7amb2VvAxdRUeFUM+jWaSQchnjRHRtk9l0p1wZ6ES5YCYUZXxRZCEmtmrh42AoRMM 6AUVWTYYIMpTExUGHdPlcTAfMYfKPnsIicavxSgLr5563bhW0mN0tR84y+Stb18tES p+QKOisroVQxsTwny5wmC1WMvoHajZEQPhWnx4A6FBBcdUG1TKx3WHO1xAoPKUTs5B 5ysmXVNF5qlaCz6GFbZeWOpOLXUXvya9SYQD9X4p/vZGiY3mzavq+FcOxBsyJBLwHk ipqu3cI432bFQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1x2UjV-00000004tRh-0iWB; Fri, 04 Sep 2026 14:17:33 +0000 Date: Fri, 04 Sep 2026 15:20:07 +0100 Message-ID: <87tso53xpk.wl-maz@kernel.org> From: Marc Zyngier To: Adrian Ng Ho Yin Cc: tglx@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4] irqchip/gic-v3: Add Altera SoCFPGA Agilex5 GIC600 DMA32 erratum workaround In-Reply-To: <20260904091114.2259616-1-adrian.ho.yin.ng@altera.com> References: <20260904091114.2259616-1-adrian.ho.yin.ng@altera.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: adrian.ho.yin.ng@altera.com, tglx@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 04 Sep 2026 10:11:14 +0100, Adrian Ng Ho Yin wrote: > > Agilex5 integrates GIC600 with an ACE-lite interface limited to a 32-bit > address bus, so the ITS can only access the first 4 GB of physical address > space. Add ALTERA_ERRATUM_AGILEX5 and register intel,socfpga-agilex5 on the > existing dma_32bit_impaired_platforms list. > > This limitation is documented as Agilex 5 ES Device Errata 2.1.23 (825514). > > Signed-off-by: Adrian Ng Ho Yin > --- > Link: https://docs.altera.com/r/docs/825514/current/agilex-5-es-device-errata-and-user-guidelines/hps-gicv3-its-and-lpi-unable-to-access-physical-memory-larger-than-32-bits-causing-msi-x-interrupt-failure > Link: https://lore.kernel.org/linux-arm-kernel/372f059069a5551ea1096015f855cc306dbd7cd4.1747368554.git.adrianhoyin.ng@altera.com/ # v1 > Link: https://lore.kernel.org/linux-arm-kernel/6a44509ca0edaabc17e59d2e27fef1c782183456.1751618484.git.adrianhoyin.ng@altera.com/ # v2 > Link: https://lore.kernel.org/linux-arm-kernel/20260622024945.21354-1-muhammad.nazim.amirul.nazle.asmade@altera.com/ # v3 (untagged) > > Changes in v4: > - Rebase onto dma_32bit_impaired_platforms shared quirk (post Renesas) > - Add ALTERA_ERRATUM_AGILEX5 Kconfig and silicon-errata entry > - Cite Agilex 5 ES Device Errata 2.1.23 > > Changes in v3: > - Extend existing Rockchip dma32 quirk path for Agilex5 > > Changes in v2: > - Drop DT binding quirk; use IIDR + of_machine_is_compatible() > > Documentation/arch/arm64/silicon-errata.rst | 3 +++ > arch/arm64/Kconfig | 10 ++++++++++ > drivers/irqchip/irq-gic-v3-its.c | 3 +++ > 3 files changed, 16 insertions(+) > > diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst > index ac3248b9f2f3..8522ba072040 100644 > --- a/Documentation/arch/arm64/silicon-errata.rst > +++ b/Documentation/arch/arm64/silicon-errata.rst > @@ -53,6 +53,9 @@ stable kernels. > | Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 | > +----------------+-----------------+-----------------+-----------------------------+ > +----------------+-----------------+-----------------+-----------------------------+ > +| Altera | SoCFPGA Agilex5 | 2.1.23 | ALTERA_ERRATUM_AGILEX5 | > ++----------------+-----------------+-----------------+-----------------------------+ > ++----------------+-----------------+-----------------+-----------------------------+ > | Ampere | AmpereOne | AC03_CPU_38 | AMPERE_ERRATUM_AC03_CPU_38 | > +----------------+-----------------+-----------------+-----------------------------+ > | Ampere | AmpereOne | AC03_CPU_57 | N/A | > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index b5a51b0ef944..e3afb591db68 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -418,6 +418,16 @@ menu "Kernel Features" > > menu "ARM errata workarounds via the alternatives framework" > > +config ALTERA_ERRATUM_AGILEX5 Is this the sole erratum on this HW? The documentation says otherwise. So please add a suffix that uniquely identifies it (something like ALTERA_ERRATUM_AGILEX5_2_1_23). > + bool "Altera Agilex5: GIC600 can not access physical addresses higher than 4GB" > + default y > + help > + The Altera SoCFPGA Agilex5 GIC600 SoC integration has ACE-lite > + addressing limited to the first 32bit of physical address space. > + This is documented as Agilex 5 ES Device Errata 2.1.23 (825514). > + > + If unsure, say Y. > + This is in the wrong place. Look where the other GIC errata are, and put it there. Also, this should be selected by ARCH_INTEL_SOCFPGA, instead of being left for the user to choose. M. -- Jazz isn't dead. It just smells funny.