From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F32B71E1DE5 for ; Sun, 26 Jul 2026 12:41:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785069714; cv=none; b=XOdWKwnrK3bAzd6AXmJmH6mvcR24mEJy102SXh7L+8bY0n8eIcpcVmZ0PuSa8bsCya4RKp4Q6BarQWi4t+jgesfKpyUQGvRlhYajFt4dQB4vdLhUKlMwQ7mb6vVM387obKThK4FHS/uYorEWvNHgKGS2j0x4p1FWwjWemW8UcYk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785069714; c=relaxed/simple; bh=0PSj/OGTxZfpEhFxtK1o87NN2EN9O3xboVLJDsMx1JM=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=cfFPex4YrXecjz+i+BRfoKUd5KR1llEyK/y25lehfMyQ4EpaaLokwCV1TB8G5c4JtUTcmjlmVb5LTl8ldtaC0jQKs/PknrA8C0GXiUgMOdsZqEzJtMbK+QNSA/ZCwvNbgeSHKpULO9MNCU53MGYZXYtGc3wuAE+YUPajUZCYkRE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=b0OjmfyO; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="b0OjmfyO" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8CC331F000E9; Sun, 26 Jul 2026 12:41:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785069712; bh=5biH2onDtuL3obuel5O14yJjmvxIh8PysG2Ka/dgiUM=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=b0OjmfyOWSB9qYRdhDb/4BdQ0Bj0xrTw1itUIGwyUj26THtEejRytD9zHoj7sOocr S/M64/3J/39aWkSM9yaynUp5DQOxle9Fq0D3Zx40+TjZAPE8nFMEKbYWJ58IngK6XQ NovOrRXNtKknsIXkgGzgFkQ5ok/nBQ7XccUKVFJoespLn8quX5fFGOtecYhNw1Z725 moPTL7HhxmZmOli4uU+ucWlNFlduyG14w1kzxaHqwEqgmHIn8wGCkILewU4t6OAoB8 wPAaVIebQJeyefsmpC5iJ1PmyXZno8H6b0BuG/8ILCIRcrYNcIMIHDPcByPMlqr59Q egfWS21TMfyqQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wnyAw-00000008wye-1d4a; Sun, 26 Jul 2026 12:41:50 +0000 Date: Sun, 26 Jul 2026 13:43:14 +0100 Message-ID: <87tsplq5ul.wl-maz@kernel.org> From: Marc Zyngier To: Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Catalin Marinas , Mark Rutland , Thomas Gleixner , Ben Horgan , Daniel Lezcano Subject: Re: [PATCH v2 0/5] arm64: arch_timer: Improve errata handling In-Reply-To: References: <20260508094203.2913880-1-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, tglx@kernel.org, ben.horgan@arm.com, daniel.lezcano@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 23 Jul 2026 12:45:01 +0100, Will Deacon wrote: > > Hi Marc, > > Sorry it took me so long to look at this. No worries, thanks for having given it a look. [...] > > I think this series is a definite improvement on the existing (broken) > code, but there are two things that jump out at me with the new code: > > 1. If somebody uses maxcpus= on perfectly working hardware, they will > run with the overhead of the workaround. I fear this will be > unpopular (and I sympathise!)... I suppose we could wait for people > to scream and then add something like a cmdline option to pinky > promise that the late CPUs are not affected by any timer errata (we > could presumably refuse to bring them online if they are?). I've now added such a command-line option, forcing the counter errata management to be disabled from boot, with a loud warning being produced if we spot that we should have applied something. > > 2. It's a bit grotty that you have to maintain your own mask to track > which CPUs have booted once. I'd have thought this information should > exist already, although none of the existing masks I could find do > quite what you need. One alternative would be to iterate our per-cpu > 'cpu_data' variable or perhaps you could even use the driver's > existing 'arch_timer_evt' variable? Sure, that's easy enough, just slower. Not that it should matter much. I'll post an updated series once I've retested the various configurations. Thanks, M. -- Jazz isn't dead. It just smells funny.