From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2CC82472A6 for ; Thu, 20 Aug 2026 08:01:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787212865; cv=none; b=diwOfrJEXlg61MfGmT/EqEW1o6UIOCb0VxXBTteIEEK1Y4cSA+olGmtdRI9kwclRRwejg/H+DIY+TP1itvNCxrLYAyRDy4tWeoL9XFCD0yhJC1pAtfMWu7QuUJZ9Ve0JGISvGvdt2s/pXKM6Ali5YkoB7HHNVl/5PZLEwko+Uo0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787212865; c=relaxed/simple; bh=GtdyMKMTrmxACvSQzhXPFbsx9qVuGI8EdPFW8Py3wcU=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=WBSR93vehk5DiGAac8ZNQQ4CsBi86W0XKBV05oNF/5Cks0AdCJc/WN6LAJFnULMoWm3F5dDmwaIiVYWRQilCp7u13WnDL/7Ly8LaRz9++6HJ8XlIWZZdQDtz04+EMmNQebt51kIOYcEntEw/3kyOtUl9mfKk4v8+yPUSMfzqFsM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dv8+wyMP; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dv8+wyMP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 93B4C1F000E9; Thu, 20 Aug 2026 08:01:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1787212864; bh=GtdyMKMTrmxACvSQzhXPFbsx9qVuGI8EdPFW8Py3wcU=; h=From:To:Cc:Subject:In-Reply-To:References:Date; b=dv8+wyMPU0yMusjhi/2auw/TfE47+38gKpC9/zkPM3shIwiJis0Mvl7T4SS8si0/M mE8SOpL5i6X3/qSOFPva6bThmSlHRqYwW/BJ+jXd0rmVK84iWCZ9xgDT6yDAGPFEwb RvHDQAjhSKEkGbR4YUGis+2KUhY126vmRLSl7rSDU3EdQ7P84HtkZ1lXkHaQ+dx2P3 xO8cJpiE5dw0L91HtKQJoiAe4bRT1Fl72k4F2jL297+CBYChYkDREkjst6J3nUvvpN z7UPHz2216f9m4pAQYIwE5lu88prd8XEixFYpZPhHte4Pam+HdiwiSvw5t5U2zSkuK xnjOXXd/4FnLA== From: Thomas Gleixner To: Alexander Wilhelm Cc: linux-kernel@vger.kernel.org, Frank Li Subject: Re: [PATCH RFC v2 0/2] irqchip/ls-scfg-msi: add multi-MSI support In-Reply-To: <20260722-irqchip-ls-scfg-msi-add-multi-msi-support-v2-0-24eb208c5d38@westermo.com> References: <20260722-irqchip-ls-scfg-msi-add-multi-msi-support-v2-0-24eb208c5d38@westermo.com> Date: Thu, 20 Aug 2026 10:01:01 +0200 Message-ID: <87v795i5ky.ffs@fw13> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Wed, Jul 22 2026 at 10:26, Alexander Wilhelm wrote: > This series enables multi-MSI (nr_irqs > 1) allocation on the Layerscape > SCFG MSI controller so PCI endpoints that request contiguous MSI vector > blocks (for example ath12k, which asks for 16 vectors: 3 MHI + 5 CE + 8 DP) > no longer fall back to single-MSI operation with all interrupts multiplexed > onto one CPU. > > The first patch is a preparation refactor: switch the hwirq bookkeeping > from find_first_zero_bit() / __set_bit() to bitmap_find_free_region() / > bitmap_release_region(), release the region on iommu_dma_prepare_msi() > error, and loop irq_domain_set_info() over nr_irqs. For the current > single-MSI case (order 0) this is functionally equivalent; the only > externally visible change is -ENOMEM instead of -ENOSPC on exhaustion. > > The second patch enables MSI_FLAG_MULTI_PCI_MSI on the parent domain, drops > the WARN_ON(nr_irqs != 1) guard, and statically pins each MSIR's chained > parent IRQ to its matching CPU in no-affinity mode. That pinning is > required because affinity mode only releases every (1 << ibs_shift)-th > hwirq and cannot satisfy aligned power-of-two allocations of size > 1; > users of multi-MSI must therefore boot with lsmsi=no-affinity. That needs eyeballs from the NXP people.