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X-CSE-ConnectionGUID: MMCKHjZjTl+3/YyFl6uevQ== X-CSE-MsgGUID: zBxcZZCoTr+Q9RnHkpclpg== X-IronPort-AV: E=McAfee;i="6700,10204,11155"; a="23832921" X-IronPort-AV: E=Sophos;i="6.09,266,1716274800"; d="scan'208";a="23832921" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2024 22:56:00 -0700 X-CSE-ConnectionGUID: f1e7N9nERyCnEP5fu5NIxQ== X-CSE-MsgGUID: KSKV4sUyRYWndxRR66R8EA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,266,1716274800"; d="scan'208";a="61021643" Received: from yhuang6-desk2.sh.intel.com (HELO yhuang6-desk2.ccr.corp.intel.com) ([10.238.208.55]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2024 22:55:57 -0700 From: "Huang, Ying" To: Jonathan Cameron Cc: Dan Williams , Dave Jiang , , , Davidlohr Bueso , "Alison Schofield" , Vishal Verma , Ira Weiny , "Alejandro Lucero" Subject: Re: [PATCH 3/3] cxl: Avoid to create dax regions for type2 accelerators In-Reply-To: <20240804173813.00001018@Huawei.com> (Jonathan Cameron's message of "Sun, 4 Aug 2024 17:38:13 +0100") References: <20240729084611.502889-1-ying.huang@intel.com> <20240729084611.502889-4-ying.huang@intel.com> <20240804173813.00001018@Huawei.com> Date: Tue, 06 Aug 2024 13:52:25 +0800 Message-ID: <87v80e9p0m.fsf@yhuang6-desk2.ccr.corp.intel.com> User-Agent: Gnus/5.13 (Gnus v5.13) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=ascii Jonathan Cameron writes: > On Mon, 29 Jul 2024 16:46:11 +0800 > Huang Ying wrote: > >> The memory range of a type2 accelerator should be managed by the type2 >> accelerator specific driver instead of the common dax region drivers, >> as discussed in [1]. >> >> [1] https://lore.kernel.org/linux-cxl/66469ff1b8fbc_2c2629427@dwillia2-xfh.jf.intel.com.notmuch/ >> >> So, in this patch, we skip dax regions creation for type2 accelerator >> device memory regions. >> >> Based on: https://lore.kernel.org/linux-cxl/168592159835.1948938.1647215579839222774.stgit@dwillia2-xfh.jf.intel.com/ >> >> Signed-off-by: "Huang, Ying" >> Co-developed-by: Dan Williams >> Signed-off-by: Dan Williams >> Cc: Davidlohr Bueso >> Cc: Jonathan Cameron >> Cc: Dave Jiang >> Cc: Alison Schofield >> Cc: Vishal Verma >> Cc: Ira Weiny >> Cc: Alejandro Lucero >> --- >> drivers/cxl/core/region.c | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c >> index 9a483c8a32fd..b37e12bb4a35 100644 >> --- a/drivers/cxl/core/region.c >> +++ b/drivers/cxl/core/region.c >> @@ -3435,6 +3435,14 @@ static int cxl_region_probe(struct device *dev) >> p->res->start, p->res->end, cxlr, >> is_system_ram) > 0) >> return 0; >> + /* >> + * HDM-D[B] (device-memory) regions have accelerator >> + * specific usage, skip device-dax registration. >> + */ >> + if (cxlr->type == CXL_DECODER_DEVMEM) >> + return 0; > > As in previous need to be careful as that may not mean it's > an accelerator. Yes. We need some other way to identify type2 devices. > However, we do need to deal with BI setup for HDM-DB type 3 devices > etc and to check the HDM Decoder capability registers to make sure > Supported Coherence model is appropriate. (e.g. 11 for host only or > device coherency - HDM-H/HDM-DB) Yes. We need to check BI configuration too. >> + >> + /* HDM-H routes to device-dax */ >> return devm_cxl_add_dax_region(cxlr); >> default: >> dev_dbg(&cxlr->dev, "unsupported region mode: %d\n", -- Best Regards, Huang, Ying