From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64E97C48BDF for ; Sun, 20 Jun 2021 11:23:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2F13C610EA for ; Sun, 20 Jun 2021 11:23:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229579AbhFTLZ2 (ORCPT ); Sun, 20 Jun 2021 07:25:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229554AbhFTLZZ (ORCPT ); Sun, 20 Jun 2021 07:25:25 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05F5AC061574 for ; Sun, 20 Jun 2021 04:23:12 -0700 (PDT) From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1624188189; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=v5bNhJoM3/FLw4Sw6281mYeD7esoBy928BpQg2VpBIY=; b=BU+N+QWnB/4dZ5yiG7ScsxJDGXXx+1aD3RaMxGM8cmmiVV4VMK4melGWva7N1V1UbjKhZP smkJG0RkRHYWg2iKWGjFCfF3nj/uqAxewGN4gWNo5z26ptzWrUmmyv27FChG0+UuIvizC4 I+13/3sAiut01kwjIbod6XuxgbWh6o/5+05XJqmICNXwdfE8r1Tp05lqSNnUnyYegs/G1p iDdaCfpp2mqKNYnsqHm9YU6QEv8v+Q0++5qTjw8zSe+kdlqD039yc8pAcwBngzhhXH3fmk AcQJK7V6oYIoDgTU5XcrDGSDZdpsvJ6ONGCNFIxkCUn6C5V2sqB+6FmYefkCow== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1624188189; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=v5bNhJoM3/FLw4Sw6281mYeD7esoBy928BpQg2VpBIY=; b=wtgM6bxF41VoEmg0ep1ScW4g4ce986W/us+H9vFBuMrHFC6Z4EwnhgY4XkMu5C0+Sb0lMN 841kTnoDdQ5MHjAg== To: Andy Lutomirski , Lai Jiangshan , Linux Kernel Mailing List Cc: Steven Rostedt , Lai Jiangshan , Ingo Molnar , Borislav Petkov , the arch/x86 maintainers , "H. Peter Anvin" , Juergen Gross , "Peter Zijlstra \(Intel\)" , Al Viro , Arvind Sankar Subject: Re: [RFC PATCH 1/4] x86/entry/nmi: Switch to the entry stack before switching to the thread stack In-Reply-To: <444d7139-e47a-4831-93d0-8eb5b9680fdc@www.fastmail.com> References: <20210601065217.23540-1-jiangshanlai@gmail.com> <20210601065217.23540-2-jiangshanlai@gmail.com> <87bl81h3ih.ffs@nanos.tec.linutronix.de> <444d7139-e47a-4831-93d0-8eb5b9680fdc@www.fastmail.com> Date: Sun, 20 Jun 2021 13:23:08 +0200 Message-ID: <87wnqog4pv.ffs@nanos.tec.linutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Jun 19 2021 at 20:13, Andy Lutomirski wrote: > On Sat, Jun 19, 2021, at 3:51 PM, Thomas Gleixner wrote: >> On Tue, Jun 01 2021 at 14:52, Lai Jiangshan wrote: >> > From: Lai Jiangshan >> > >> > Current kernel has no code to enforce data breakpoint not on the thread >> > stack. If there is any data breakpoint on the top area of the thread >> > stack, there might be problem. >>=20 >> And because the kernel does not prevent data breakpoints on the thread >> stack we need to do more complicated things in the already horrible >> entry code instead of just doing the obvious and preventing data >> breakpoints on the thread stack? > > Preventing breakpoints on the thread stack is a bit messy: it=E2=80=99s > possible for a breakpoint to be set before the address in question is > allocated for the thread stack. Bah. > None of this is NMI-specific. #DB itself has the same problem. Oh well. > We could plausibly solve it differently by disarming breakpoints in > the entry asm before switching stacks. I=E2=80=99m not sure how much I li= ke > that approach. That's ugly and TBH in some sense is a breakpoint on the thread stack a violation of noinstr. I rather see them prevented completely, but yes that would have to be expanded to pretty much any variable which is touched in noinstr sections. What a mess. Thanks, tglx