From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27BACC433DB for ; Wed, 27 Jan 2021 21:14:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DCBD064DA1 for ; Wed, 27 Jan 2021 21:14:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234014AbhA0VOJ (ORCPT ); Wed, 27 Jan 2021 16:14:09 -0500 Received: from Galois.linutronix.de ([193.142.43.55]:58884 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234006AbhA0VOF (ORCPT ); Wed, 27 Jan 2021 16:14:05 -0500 From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1611781993; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=+W210YcTn7f0FWj77TkJ8ytVhpV8sXey/lss5LyxnfI=; b=k7/Y8grAb9UaDQcEUoXliwbIZC+AonOYgpVzhs4Dwl6y3yyGTvk5N0SmGeuAZZHertjRqB vZ7DVk44GvLgOSqre4gguTCBOyocGAaggHaEnulk0hV1DkR/KGfdqcV2L8mnWox9KeB93i GPbdXITDeJYQWqVjb7GbiRLW7BeeyzIpUbTwjabdVyjLuxfAHaCaF1tRkZUJpP+lnSypca niX090nP3DUqMfIQYPTy7UkVTOoVuvRxo6NXwtVbrHiLZ/OXjeJ6UwDEdoPEBRnHWFqrX7 +GpmOpocO9uj6OwQtA//9x6SzKRSgNPQqNC+JYVJSb5I0jkIPJxw4cGLlbAyng== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1611781993; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=+W210YcTn7f0FWj77TkJ8ytVhpV8sXey/lss5LyxnfI=; b=b9D9bjVVs3raMgxd5T2FRNvlUnF+A4noFc7+OsN1Ro2JVmVfoDAp13VJOvO1Nbgcdw8Fd3 2SnYec6CKsOHwWBg== To: Fenghua Yu , Borislav Petkov , Ingo Molnar , Peter Zijlstra , Tony Luck , Randy Dunlap , Xiaoyao Li , Ravi V Shankar Cc: linux-kernel , x86 , Fenghua Yu Subject: Re: [PATCH v4 1/4] x86/cpufeatures: Enumerate #DB for bus lock detection In-Reply-To: <20201124205245.4164633-2-fenghua.yu@intel.com> References: <20201124205245.4164633-1-fenghua.yu@intel.com> <20201124205245.4164633-2-fenghua.yu@intel.com> Date: Wed, 27 Jan 2021 22:13:13 +0100 Message-ID: <87wnvydqxi.fsf@nanos.tec.linutronix.de> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Nov 24 2020 at 20:52, Fenghua Yu wrote: > A bus lock is acquired though either split locked access to > writeback (WB) memory or any locked access to non-WB memory. This is > typically >1000 cycles slower than an atomic operation within a cache > line. It also disrupts performance on other cores. > > Some CPUs have ability to notify the kernel by an #DB trap after a user > instruction acquires a bus lock and is executed. This allows the kernel > to enforce user application throttling or mitigations. That's nice, but how does that interact with a data breakpoint on the same location? Also the information you pointed to in the cover letter > [1] Intel Instruction Set Extension Chapter 8: > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf does not contain anything which is even remotely related to this patch series. That chapter describes another bit in TEST_CTRL_MSR ... Thanks, tglx