From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755421AbcECJO4 (ORCPT ); Tue, 3 May 2016 05:14:56 -0400 Received: from e23smtp01.au.ibm.com ([202.81.31.143]:33092 "EHLO e23smtp01.au.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750728AbcECJOy (ORCPT ); Tue, 3 May 2016 05:14:54 -0400 X-IBM-Helo: d23dlp02.au.ibm.com X-IBM-MailFrom: aneesh.kumar@linux.vnet.ibm.com X-IBM-RcptTo: linux-kernel@vger.kernel.org From: "Aneesh Kumar K.V" To: Valentin Rothberg , mpe@ellerman.id.au Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Valentin Rothberg Subject: Re: [PATCH] powerpc/mm/radix: fix STD_MMU_64 typo In-Reply-To: <1462258767-83025-1-git-send-email-valentinrothberg@gmail.com> References: <1462258767-83025-1-git-send-email-valentinrothberg@gmail.com> User-Agent: Notmuch/0.21 (http://notmuchmail.org) Emacs/24.5.1 (x86_64-pc-linux-gnu) Date: Tue, 03 May 2016 14:43:48 +0530 Message-ID: <87zis7y04z.fsf@skywalker.in.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16050309-1618-0000-0000-0000459A147A Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Valentin Rothberg writes: > s/MMU_STD_64/STD_MMU_64/ > > Fixes: 11ffc1cfa4c2 ("powerpc/mm/radix: Use STD_MMU_64 to properly > isolate hash related code") > Signed-off-by: Valentin Rothberg Reviewed-by: Aneesh Kumar K.V > --- > > I only compile tested this change. The issue has been detected with > scripts/checkkconfigsymbols.py > > arch/powerpc/kernel/mce_power.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c > index bec70338672e..7353991c4ece 100644 > --- a/arch/powerpc/kernel/mce_power.c > +++ b/arch/powerpc/kernel/mce_power.c > @@ -80,7 +80,7 @@ void __flush_tlb_power9(unsigned int action) > > > /* flush SLBs and reload */ > -#ifdef CONFIG_PPC_MMU_STD_64 > +#ifdef CONFIG_PPC_STD_MMU_64 > static void flush_and_reload_slb(void) > { > struct slb_shadow *slb; > @@ -125,7 +125,7 @@ static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits) > * reset the error bits whenever we handle them so that at the end > * we can check whether we handled all of them or not. > * */ > -#ifdef CONFIG_PPC_MMU_STD_64 > +#ifdef CONFIG_PPC_STD_MMU_64 > if (dsisr & slb_error_bits) { > flush_and_reload_slb(); > /* reset error bits */ > @@ -157,7 +157,7 @@ static long mce_handle_common_ierror(uint64_t srr1) > switch (P7_SRR1_MC_IFETCH(srr1)) { > case 0: > break; > -#ifdef CONFIG_PPC_MMU_STD_64 > +#ifdef CONFIG_PPC_STD_MMU_64 > case P7_SRR1_MC_IFETCH_SLB_PARITY: > case P7_SRR1_MC_IFETCH_SLB_MULTIHIT: > /* flush and reload SLBs for SLB errors. */ > @@ -184,7 +184,7 @@ static long mce_handle_ierror_p7(uint64_t srr1) > > handled = mce_handle_common_ierror(srr1); > > -#ifdef CONFIG_PPC_MMU_STD_64 > +#ifdef CONFIG_PPC_STD_MMU_64 > if (P7_SRR1_MC_IFETCH(srr1) == P7_SRR1_MC_IFETCH_SLB_BOTH) { > flush_and_reload_slb(); > handled = 1; > @@ -332,7 +332,7 @@ static long mce_handle_ierror_p8(uint64_t srr1) > > handled = mce_handle_common_ierror(srr1); > > -#ifdef CONFIG_PPC_MMU_STD_64 > +#ifdef CONFIG_PPC_STD_MMU_64 > if (P7_SRR1_MC_IFETCH(srr1) == P8_SRR1_MC_IFETCH_ERAT_MULTIHIT) { > flush_and_reload_slb(); > handled = 1; > -- > 2.7.4