From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751244AbeAYQJE (ORCPT ); Thu, 25 Jan 2018 11:09:04 -0500 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:42658 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750851AbeAYQJD (ORCPT ); Thu, 25 Jan 2018 11:09:03 -0500 From: Philippe CORNU To: Yannick FERTRE , Benjamin Gaignard , Vincent ABRIOU , "David Airlie" , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre TORGUE , "dri-devel@lists.freedesktop.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" CC: Mickael REULIER , Gabriel FERNANDEZ , Ludovic BARRE Subject: Re: [PATCH] dt-bindings: display: stm32: add pixel clock mandatory property Thread-Topic: [PATCH] dt-bindings: display: stm32: add pixel clock mandatory property Thread-Index: AQHTk5cFTjeGZ3/jcUi7iLjy9kXAeaOEtY2A Date: Thu, 25 Jan 2018 16:08:35 +0000 Message-ID: <881ad794-6c4a-b753-2325-ac8522f8a70c@st.com> References: <20180122153805.23720-1-philippe.cornu@st.com> In-Reply-To: <20180122153805.23720-1-philippe.cornu@st.com> Accept-Language: fr-FR, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: user-agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.50] Content-Type: text/plain; charset="utf-8" Content-ID: <3D1B921D3DD10848B9A059E8980C9881@st.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2018-01-25_06:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id w0PG997M032209 Hi, in short: this patch is "CANCELLED" : ) There is no need to add the pixel clock as a mandatory property because now the clock value is ajusted in adjusted_mode. Please have a look to patches: - drm/stm: ltdc: use crtc_mode_fixup to update adjusted_mode clock - drm/bridge/synopsys: dsi: use adjusted_mode in mode_set Hope it is better, comments are welcome Many thanks, Philippe :-) On 01/22/2018 04:38 PM, Philippe Cornu wrote: > Add the DPI/RGB input pixel clock in mandatory properties > because it really offers a better preciseness for timing > computations. > > Signed-off-by: Philippe Cornu > --- > Please apply "dt-bindings: display: stm32: correct clock-names > in dsi panel example" before this patch. > > Changes in v3: remove the note regarding swapped clock names > (now in a separate patch). > Changes in v2: put new clock in last position (Rob Herring) > > Documentation/devicetree/bindings/display/st,stm32-ltdc.txt | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt > index 3eb1b48b47dd..942b7237ae87 100644 > --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt > +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt > @@ -29,6 +29,7 @@ Mandatory properties specific to STM32 DSI: > - compatible: "st,stm32-dsi". > - clock-names: > - phy pll reference clock string name, must be "ref". > + - DPI/RGB input pixel clock string name, must be "px_clk". > - resets: see [5]. > - reset-names: see [5]. > > @@ -97,8 +98,9 @@ Example 2: DSI panel > #size-cells = <0>; > compatible = "st,stm32-dsi"; > reg = <0x40016c00 0x800>; > - clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>; > - clock-names = "pclk", "ref"; > + clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>, > + <&rcc 1 CLK_LCD>; > + clock-names = "pclk", "ref", "px_clk"; > resets = <&rcc STM32F4_APB2_RESET(DSI)>; > reset-names = "apb"; > >