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<882ec9f1-2a6c-49c4-8f36-9682c551f8b6@nvidia.com> Date: Thu, 21 May 2026 09:54:09 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/2] PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance latency To: Bjorn Helgaas Cc: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, thierry.reding@gmail.com, jonathanh@nvidia.com, kishon@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, Frank.Li@nxp.com, den@valinux.co.jp, hongxing.zhu@nxp.com, jingoohan1@gmail.com, vidyas@nvidia.com, cassel@kernel.org, 18255117159@163.com, linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260520193024.GA84903@bhelgaas> Content-Language: en-US X-Nvconfidentiality: public From: Manikanta Maddireddy In-Reply-To: <20260520193024.GA84903@bhelgaas> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit 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=?utf-8?B?UmkwcG0vNHdLaEg4aS8vVkgzcFF2bEJaKzBlZ3lFcmhwVEs3SGlYQT09?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: e12b3c77-07c9-4fab-24ea-08deb6f0d3f3 X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB8245.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 04:24:20.1969 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: GW3wa+QI/hiTGbFBtV+Zm7ZVds2H5QgEI3xI7w67CobnBNIwe/CVbeImV7QXn20aE6Srv9Eci/lSx3FRRXVWuQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8644 On 21/05/26 1:00 am, Bjorn Helgaas wrote: > On Fri, May 15, 2026 at 12:37:52PM +0530, Manikanta Maddireddy wrote: >> Program the Synopsys DesignWare PORT_AFR L1 entrance latency field from the >> optional aspm-l1-entry-delay-ns device tree property (nanoseconds). >> >> Convert delay to whole microseconds with ceiling division (DIV_ROUND_UP), >> then derive the 3-bit hw encoding as the minimum of order_base_2(us) and 7. >> If the property is not present or cannot be read, default to 7. >> >> Hardware encoding (PORT_AFR L1 entrance latency, bits 27:29): >> >> +--------------------------+----------+ >> | Advertised maximum | Code | >> +--------------------------+----------+ >> | Maximum of 1 us | 000b | >> +--------------------------+----------+ >> | Maximum of 2 us | 001b | >> +--------------------------+----------+ >> | Maximum of 4 us | 010b | >> +--------------------------+----------+ >> | Maximum of 8 us | 011b | >> +--------------------------+----------+ >> | Maximum of 16 us | 100b | >> +--------------------------+----------+ >> | Maximum of 32 us | 101b | >> +--------------------------+----------+ >> | Maximum of 64 us | 110b | >> +--------------------------+----------+ >> | Rest | 111b | >> +--------------------------+----------+ >> >> Signed-off-by: Manikanta Maddireddy >> --- >> V2: Fixed commit message as per review comments. >> V3: Fixed encoding to handle all cases per above table. >> >> drivers/pci/controller/dwc/pcie-tegra194.c | 13 +++++++++++++ >> 1 file changed, 13 insertions(+) >> >> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c >> index 9dcfa194050e..5309a2f1356d 100644 >> --- a/drivers/pci/controller/dwc/pcie-tegra194.c >> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c >> @@ -272,6 +272,7 @@ struct tegra_pcie_dw { >> u32 aspm_cmrt; >> u32 aspm_pwr_on_t; >> u32 aspm_l0s_enter_lat; >> + u32 aspm_l1_enter_lat; >> >> struct regulator *pex_ctl_supply; >> struct regulator *slot_ctl_3v3; >> @@ -715,6 +716,8 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie) >> val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); >> val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK; >> val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); >> + val &= ~PORT_AFR_L1_ENTRANCE_LAT_MASK; >> + val |= (pcie->aspm_l1_enter_lat << PORT_AFR_L1_ENTRANCE_LAT_SHIFT); > > Thanks for your patch! > > I think follow-on patches could use FIELD_MODIFY() for > PORT_AFR_L1_ENTRANCE_LAT_MASK and PORT_AFR_L0S_ENTRANCE_LAT_MASK. > > It would be good to remove all these _SHIFT #defines in a future patch, > if possible: > > PORT_AFR_L0S_ENTRANCE_LAT_SHIFT > PORT_AFR_L1_ENTRANCE_LAT_SHIFT > GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT > PCIE_MSIX_DOORBELL_PF_SHIFT > EVENT_COUNTER_ENABLE_SHIFT > EVENT_COUNTER_EVENT_SEL_SHIFT > EVENT_COUNTER_GROUP_SEL_SHIFT > > The uses can probably be replaced with FIELD_MODIFY() and > FIELD_PREP(), possibly with the addition of a _MASK #define or two. > Noted, I will send a patch to remove all _SHIFT #defines. Thanks, Manikanta >> val |= PORT_AFR_ENTER_ASPM; >> dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); >> } >> @@ -1115,6 +1118,7 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie) >> { >> struct platform_device *pdev = to_platform_device(pcie->dev); >> struct device_node *np = pcie->dev->of_node; >> + u32 val; >> int ret; >> >> pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); >> @@ -1141,6 +1145,15 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie) >> dev_info(pcie->dev, >> "Failed to read ASPM L0s Entrance latency: %d\n", ret); >> >> + /* Default to max latency of 7. */ >> + pcie->aspm_l1_enter_lat = 7; >> + ret = of_property_read_u32(np, "aspm-l1-entry-delay-ns", &val); >> + if (!ret) { >> + u32 us = DIV_ROUND_UP(val, 1000); >> + >> + pcie->aspm_l1_enter_lat = min_t(u32, order_base_2(us), 7); >> + } >> + >> ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes); >> if (ret < 0) { >> dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret); >> -- >> 2.34.1 >> -- nvpublic