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Tue, 11 Feb 2025 01:51:24 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51B1pNme021339 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 11 Feb 2025 01:51:23 GMT Received: from [10.134.70.212] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 10 Feb 2025 17:51:23 -0800 Message-ID: <887a8c60-ef53-4f46-9dd1-c74f266f8bb2@quicinc.com> Date: Mon, 10 Feb 2025 17:51:07 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] drm/msm/dsi: Use existing per-interface slice count in DSC timing Content-Language: en-US To: Marijn Suijten , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , "David Airlie" , Vinod Koul , Simona Vetter CC: , , , , "Jordan Crouse" , <~postmarketos/upstreaming@lists.sr.ht>, AngeloGioacchino Del Regno , "Martin Botka" , Jami Kettunen , Konrad Dybcio References: <20250209-drm-msm-initial-dualpipe-dsc-fixes-v2-0-9a60184fdc36@somainline.org> <20250209-drm-msm-initial-dualpipe-dsc-fixes-v2-1-9a60184fdc36@somainline.org> From: Jessica Zhang In-Reply-To: <20250209-drm-msm-initial-dualpipe-dsc-fixes-v2-1-9a60184fdc36@somainline.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: WVlzP2eybIJaV7B7JPZcca6eFxe4rx8v X-Proofpoint-ORIG-GUID: WVlzP2eybIJaV7B7JPZcca6eFxe4rx8v X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-11_01,2025-02-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 clxscore=1011 suspectscore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 malwarescore=0 spamscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502110009 On 2/9/2025 1:42 PM, Marijn Suijten wrote: > When configuring the timing of DSI hosts (interfaces) in > dsi_timing_setup() all values written to registers are taking > bonded-mode into account by dividing the original mode width by 2 > (half the data is sent over each of the two DSI hosts), but the full > width instead of the interface width is passed as hdisplay parameter to > dsi_update_dsc_timing(). > > Currently only msm_dsc_get_slices_per_intf() is called within > dsi_update_dsc_timing() with the `hdisplay` argument which clearly > documents that it wants the width of a single interface (which, again, > in bonded DSI mode is half the total width of the mode) resulting in all > subsequent values to be completely off. > > However, as soon as we start to pass the halved hdisplay > into dsi_update_dsc_timing() we might as well discard > msm_dsc_get_slices_per_intf() since the value it calculates is already > available in dsc->slice_count which is per-interface by the current > design of MSM DPU/DSI implementations and their use of the DRM DSC > helpers. > > Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration") > Signed-off-by: Marijn Suijten Hi Marijn, Reviewed-by: Jessica Zhang Thanks, Jessica Zhang > --- > drivers/gpu/drm/msm/dsi/dsi_host.c | 8 ++++---- > drivers/gpu/drm/msm/msm_dsc_helper.h | 11 ----------- > 2 files changed, 4 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c > index 007311c21fdaa0462b05d53cd8a2aad0269b1727..42e100a8adca09d7b55afce0e2553e76d898744f 100644 > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c > @@ -846,7 +846,7 @@ static void dsi_ctrl_enable(struct msm_dsi_host *msm_host, > dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0)); > } > > -static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay) > +static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode) > { > struct drm_dsc_config *dsc = msm_host->dsc; > u32 reg, reg_ctrl, reg_ctrl2; > @@ -858,7 +858,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod > /* first calculate dsc parameters and then program > * compress mode registers > */ > - slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay); > + slice_per_intf = dsc->slice_count; > > total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; > bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */ > @@ -991,7 +991,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) > > if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { > if (msm_host->dsc) > - dsi_update_dsc_timing(msm_host, false, mode->hdisplay); > + dsi_update_dsc_timing(msm_host, false); > > dsi_write(msm_host, REG_DSI_ACTIVE_H, > DSI_ACTIVE_H_START(ha_start) | > @@ -1012,7 +1012,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) > DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); > } else { /* command mode */ > if (msm_host->dsc) > - dsi_update_dsc_timing(msm_host, true, mode->hdisplay); > + dsi_update_dsc_timing(msm_host, true); > > /* image data and 1 byte write_memory_start cmd */ > if (!msm_host->dsc) > diff --git a/drivers/gpu/drm/msm/msm_dsc_helper.h b/drivers/gpu/drm/msm/msm_dsc_helper.h > index b9049fe1e2790703a6f42dd7e6cd3fa5eea29389..63f95523b2cbb48f822210ac47cdd3526f231a89 100644 > --- a/drivers/gpu/drm/msm/msm_dsc_helper.h > +++ b/drivers/gpu/drm/msm/msm_dsc_helper.h > @@ -12,17 +12,6 @@ > #include > #include > > -/** > - * msm_dsc_get_slices_per_intf() - calculate number of slices per interface > - * @dsc: Pointer to drm dsc config struct > - * @intf_width: interface width in pixels > - * Returns: Integer representing the number of slices for the given interface > - */ > -static inline u32 msm_dsc_get_slices_per_intf(const struct drm_dsc_config *dsc, u32 intf_width) > -{ > - return DIV_ROUND_UP(intf_width, dsc->slice_width); > -} > - > /** > * msm_dsc_get_bytes_per_line() - calculate bytes per line > * @dsc: Pointer to drm dsc config struct > > -- > 2.48.1 > >