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Wysocki" , Lee Jones , Shawn Guo , Sascha Hauer , Fabio Estevam , Dong Aisheng , Jacky Bai , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, NXP S32 Linux Team , Christophe Lizzi , Alberto Ruiz , Enric Balletbo , Pengutronix Kernel Team , imx@lists.linux.dev References: <20241101080614.1070819-1-andrei.stefanescu@oss.nxp.com> <20241101080614.1070819-4-andrei.stefanescu@oss.nxp.com> Content-Language: en-US From: Andrei Stefanescu In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-ClientProxiedBy: AS4P191CA0026.EURP191.PROD.OUTLOOK.COM (2603:10a6:20b:5d9::17) To AM9PR04MB8487.eurprd04.prod.outlook.com (2603:10a6:20b:41a::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM9PR04MB8487:EE_|DB9PR04MB10034:EE_ X-MS-Office365-Filtering-Correlation-Id: 57243fe6-6677-4d02-0955-08dcfcc487ac X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|366016; 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Therefore, the old >> pinctrl node is deprecated. Move the pinctrl related properties >> inside the new "nxp-siul2" node. The latter one is now used >> to represent the mfd device. > > Generally, dt team want you to keep both for sometime to keep > back compatiblity. Just to make sure I understand correctly, I will keep the previous pinctrl node and have both the new siul2 node and the old pinctrl one, right? Best regards, Andrei > > Frank >> >> Signed-off-by: Andrei Stefanescu >> --- >> arch/arm64/boot/dts/freescale/s32g2.dtsi | 26 +++++++++++------------- >> arch/arm64/boot/dts/freescale/s32g3.dtsi | 26 +++++++++++------------- >> 2 files changed, 24 insertions(+), 28 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi >> index fa054bfe7d5c..e14ce5503e1f 100644 >> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi >> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi >> @@ -114,20 +114,18 @@ soc@0 { >> #size-cells = <1>; >> ranges = <0 0 0 0x80000000>; >> >> - pinctrl: pinctrl@4009c240 { >> - compatible = "nxp,s32g2-siul2-pinctrl"; >> - /* MSCR0-MSCR101 registers on siul2_0 */ >> - reg = <0x4009c240 0x198>, >> - /* MSCR112-MSCR122 registers on siul2_1 */ >> - <0x44010400 0x2c>, >> - /* MSCR144-MSCR190 registers on siul2_1 */ >> - <0x44010480 0xbc>, >> - /* IMCR0-IMCR83 registers on siul2_0 */ >> - <0x4009ca40 0x150>, >> - /* IMCR119-IMCR397 registers on siul2_1 */ >> - <0x44010c1c 0x45c>, >> - /* IMCR430-IMCR495 registers on siul2_1 */ >> - <0x440110f8 0x108>; >> + siul2: siul2@4009c000 { >> + compatible = "nxp,s32g2-siul2"; >> + reg = <0x4009c000 0x179c>, >> + <0x44010000 0x17b0>; >> + reg-names = "siul20", "siul21"; >> + gpio-controller; >> + #gpio-cells = <2>; >> + gpio-ranges = <&siul2 0 0 102>, <&siul2 112 112 79>; >> + gpio-reserved-ranges = <102 10>, <123 21>; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + interrupts = ; >> >> jtag_pins: jtag-pins { >> jtag-grp0 { >> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi >> index b4226a9143c8..fa43d036686f 100644 >> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi >> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi >> @@ -171,20 +171,18 @@ soc@0 { >> #size-cells = <1>; >> ranges = <0 0 0 0x80000000>; >> >> - pinctrl: pinctrl@4009c240 { >> - compatible = "nxp,s32g2-siul2-pinctrl"; >> - /* MSCR0-MSCR101 registers on siul2_0 */ >> - reg = <0x4009c240 0x198>, >> - /* MSCR112-MSCR122 registers on siul2_1 */ >> - <0x44010400 0x2c>, >> - /* MSCR144-MSCR190 registers on siul2_1 */ >> - <0x44010480 0xbc>, >> - /* IMCR0-IMCR83 registers on siul2_0 */ >> - <0x4009ca40 0x150>, >> - /* IMCR119-IMCR397 registers on siul2_1 */ >> - <0x44010c1c 0x45c>, >> - /* IMCR430-IMCR495 registers on siul2_1 */ >> - <0x440110f8 0x108>; >> + siul2: siul2@4009c000 { >> + compatible = "nxp,s32g3-siul2"; >> + reg = <0x4009c000 0x179c>, >> + <0x44010000 0x17b0>; >> + reg-names = "siul20", "siul21"; >> + gpio-controller; >> + #gpio-cells = <2>; >> + gpio-ranges = <&siul2 0 0 102>, <&siul2 112 112 79>; >> + gpio-reserved-ranges = <102 10>, <123 21>; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + interrupts = ; >> >> jtag_pins: jtag-pins { >> jtag-grp0 { >> -- >> 2.45.2 >>