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Fri, 11 Oct 2024 14:07:40 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 11 Oct 2024 14:07:39 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 11 Oct 2024 14:07:39 -0500 Received: from [10.249.42.149] ([10.249.42.149]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49BJ7dLe129223; Fri, 11 Oct 2024 14:07:39 -0500 Message-ID: <89091165-74d1-442a-ab34-8e70f1a2d65b@ti.com> Date: Fri, 11 Oct 2024 14:07:39 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RESEND 1/2] gpio: omap: Add omap_gpio_disable/enable_irq calls To: Judith Mendez , Santosh Shilimkar , Kevin Hilman , Linus Walleij , Bartosz Golaszewski CC: , , , Bin Liu , References: <20241011173356.870883-1-jm@ti.com> <20241011173356.870883-2-jm@ti.com> Content-Language: en-US From: Andrew Davis In-Reply-To: <20241011173356.870883-2-jm@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea On 10/11/24 12:33 PM, Judith Mendez wrote: > Add omap_gpio_disable_irq and omap_gpio_enable_irq > calls in gpio-omap. > > Currently, kernel cannot disable gpio interrupts in > case of a irq storm, so add omap_gpio_disable_irq > so that interrupts can be disabled/enabled. > > Signed-off-by: Bin Liu > Signed-off-by: Judith Mendez > --- > drivers/gpio/gpio-omap.c | 29 +++++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c > index 76d5d87e9681..913e6ece1238 100644 > --- a/drivers/gpio/gpio-omap.c > +++ b/drivers/gpio/gpio-omap.c > @@ -711,6 +711,31 @@ static void omap_gpio_unmask_irq(struct irq_data *d) > raw_spin_unlock_irqrestore(&bank->lock, flags); > } > > +static void omap_gpio_set_irq(struct irq_data *d, bool enable) > +{ > + struct gpio_bank *bank = omap_irq_data_get_bank(d); > + unsigned int offset = d->hwirq; > + unsigned long flags; > + > + raw_spin_lock_irqsave(&bank->lock, flags); > + omap_set_gpio_irqenable(bank, offset, enable); > + raw_spin_unlock_irqrestore(&bank->lock, flags); > +} > + > +static void omap_gpio_disable_irq(struct irq_data *d) > +{ > + bool enable = 1; > + > + omap_gpio_set_irq(d, !enable); Seems like an odd way to make "false", why not: omap_gpio_set_irq(d, false); Andrew > +} > + > +static void omap_gpio_enable_irq(struct irq_data *d) > +{ > + bool enable = 1; > + > + omap_gpio_set_irq(d, enable); > +} > + > static void omap_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p) > { > struct gpio_bank *bank = omap_irq_data_get_bank(d); > @@ -723,6 +748,8 @@ static const struct irq_chip omap_gpio_irq_chip = { > .irq_shutdown = omap_gpio_irq_shutdown, > .irq_mask = omap_gpio_mask_irq, > .irq_unmask = omap_gpio_unmask_irq, > + .irq_disable = omap_gpio_disable_irq, > + .irq_enable = omap_gpio_enable_irq, > .irq_set_type = omap_gpio_irq_type, > .irq_set_wake = omap_gpio_wake_enable, > .irq_bus_lock = omap_gpio_irq_bus_lock, > @@ -737,6 +764,8 @@ static const struct irq_chip omap_gpio_irq_chip_nowake = { > .irq_shutdown = omap_gpio_irq_shutdown, > .irq_mask = omap_gpio_mask_irq, > .irq_unmask = omap_gpio_unmask_irq, > + .irq_disable = omap_gpio_disable_irq, > + .irq_enable = omap_gpio_enable_irq, > .irq_set_type = omap_gpio_irq_type, > .irq_bus_lock = omap_gpio_irq_bus_lock, > .irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,