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[89.212.118.115]) by smtp.gmail.com with ESMTPSA id n37-20020a05600c3ba500b0038cc9d6ff5bsm14748150wms.4.2022.04.10.03.14.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Apr 2022 03:14:18 -0700 (PDT) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Sandor Yu , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, andrzej.hajda@intel.com, robert.foss@linaro.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, hverkuil-cisco@xs4all.nl, Neil Armstrong Cc: shengjiu.wang@nxp.com, cai.huoqing@linux.dev, maxime@cerno.tech, harry.wentland@amd.com Subject: Re: [PATCH v2 4/5] drm: bridge: dw_hdmi: add reset function for PHY GEN1 Date: Sun, 10 Apr 2022 12:14:17 +0200 Message-ID: <8917523.CDJkKcVGEf@jernej-laptop> In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Dne petek, 08. april 2022 ob 14:22:52 CEST je Neil Armstrong napisal(a): > On 08/04/2022 12:32, Sandor Yu wrote: > > PHY reset register(MC_PHYRSTZ) active high reset control for PHY GEN2, > > and active low reset control for PHY GEN1. > > > > Rename function dw_hdmi_phy_reset to dw_hdmi_phy_gen2_reset. > > Add dw_hdmi_phy_gen1_reset function for PHY GEN1. > > > > Signed-off-by: Sandor Yu > > --- > > > > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 14 +++++++++++--- > > drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 2 +- > > include/drm/bridge/dw_hdmi.h | 4 +++- > > 3 files changed, 15 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c > > b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index > > 5a7ec066e37a..13270d96e5be 100644 > > --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c > > +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c > > @@ -1369,13 +1369,21 @@ static void > > dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)> > > HDMI_PHY_CONF0_SELDIPIF_MASK); > > > > } > > > > -void dw_hdmi_phy_reset(struct dw_hdmi *hdmi) > > +void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi) > > +{ > > + /* PHY reset. The reset signal is active low on Gen1 PHYs. */ > > + hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); > > + hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); > > +} > > +EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen1_reset); > > + > > +void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi) > > > > { > > > > /* PHY reset. The reset signal is active high on Gen2 PHYs. */ > > hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); > > hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); > > > > } > > > > -EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset); > > +EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_reset); > > > > void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) > > { > > > > @@ -1529,7 +1537,7 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, > > > > if (phy->has_svsret) > > > > dw_hdmi_phy_enable_svsret(hdmi, 1); > > > > - dw_hdmi_phy_reset(hdmi); > > + dw_hdmi_phy_gen2_reset(hdmi); > > > > hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); > > > > diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c > > b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c index 5e2b0175df36..2860e6bff8b7 > > 100644 > > --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c > > +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c > > @@ -135,7 +135,7 @@ static int sun8i_hdmi_phy_config_a83t(struct dw_hdmi > > *hdmi,> > > dw_hdmi_phy_gen2_txpwron(hdmi, 0); > > dw_hdmi_phy_gen2_pddq(hdmi, 1); > > > > - dw_hdmi_phy_reset(hdmi); > > + dw_hdmi_phy_gen2_reset(hdmi); > > > > dw_hdmi_phy_gen2_pddq(hdmi, 0); > > > > diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h > > index 2a1f85f9a8a3..70082f80a8c8 100644 > > --- a/include/drm/bridge/dw_hdmi.h > > +++ b/include/drm/bridge/dw_hdmi.h > > @@ -187,9 +187,11 @@ void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, > > u8 address);> > > void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, > > > > unsigned char addr); > > > > +void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi); > > + > > > > void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable); > > void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable); > > > > -void dw_hdmi_phy_reset(struct dw_hdmi *hdmi); > > +void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi); > > > > enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, > > > > void *data); > > Reviewed-by: Neil Armstrong Acked-by: Jernej Skrabec Best regards, Jernej > > If a sun4i drm maintainer can ack, then it would be all good to apply. > > Neil