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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abbac781b78sm823562366b.60.2025.02.21.03.49.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 Feb 2025 03:49:25 -0800 (PST) Message-ID: <8936f8a7-5bc0-417b-a719-806f1ce0904b@oss.qualcomm.com> Date: Fri, 21 Feb 2025 12:49:21 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10 3/6] dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions To: Manikanta Mylavarapu , andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, catalin.marinas@arm.com, will@kernel.org, p.zabel@pengutronix.de, richardcochran@gmail.com, geert+renesas@glider.be, dmitry.baryshkov@linaro.org, arnd@arndb.de, nfraprado@collabora.com, quic_tdas@quicinc.com, biju.das.jz@bp.renesas.com, elinor.montmasson@savoirfairelinux.com, ross.burton@arm.com, javier.carrasco@wolfvision.net, quic_anusha@quicinc.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org Cc: quic_srichara@quicinc.com, quic_varada@quicinc.com References: <20250221101426.776377-1-quic_mmanikan@quicinc.com> <20250221101426.776377-4-quic_mmanikan@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250221101426.776377-4-quic_mmanikan@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: aPafMs9-vW1blERqxYA5x0I9GJcZK61f X-Proofpoint-GUID: aPafMs9-vW1blERqxYA5x0I9GJcZK61f X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-21_03,2025-02-20_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 phishscore=0 mlxlogscore=839 bulkscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502210087 On 21.02.2025 11:14 AM, Manikanta Mylavarapu wrote: > From: Devi Priya > > Add NSSCC clock and reset definitions for ipq9574. > > Reviewed-by: Krzysztof Kozlowski > Signed-off-by: Devi Priya > Signed-off-by: Manikanta Mylavarapu > --- [...] > + - | > + #include > + #include > + clock-controller@39b00000 { > + compatible = "qcom,ipq9574-nsscc"; > + reg = <0x39b00000 0x80000>; > + clocks = <&xo_board_clk>, > + <&cmn_pll NSS_1200MHZ_CLK>, > + <&cmn_pll PPE_353MHZ_CLK>, > + <&gcc GPLL0_OUT_AUX>, > + <&uniphy 0>, > + <&uniphy 1>, > + <&uniphy 2>, > + <&uniphy 3>, > + <&uniphy 4>, > + <&uniphy 5>, > + <&gcc GCC_NSSCC_CLK>; > + clock-names = "xo", > + "nss_1200", > + "ppe_353", > + "gpll0_out", > + "uniphy0_rx", > + "uniphy0_tx", > + "uniphy1_rx", > + "uniphy1_tx", > + "uniphy2_rx", > + "uniphy2_tx", > + "nsscc"; I see that the input clock is named rather non-descriptively, but maybe we should call it something like "bus" so that it has more meaning to the reader Konrad