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[192.35.156.11]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-27ed66d3acfsm66321885ad.20.2025.09.26.17.26.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 26 Sep 2025 17:26:15 -0700 (PDT) Message-ID: <89375a6d-782f-8b89-bf16-1d13b7a525ed@oss.qualcomm.com> Date: Fri, 26 Sep 2025 17:26:14 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v3 07/10] phy: qualcomm: qmp-combo: Update QMP PHY with Glymur settings Content-Language: en-US To: Dmitry Baryshkov Cc: krzk+dt@kernel.org, conor+dt@kernel.org, kishon@kernel.org, vkoul@kernel.org, gregkh@linuxfoundation.org, robh@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250925022850.4133013-1-wesley.cheng@oss.qualcomm.com> <20250925022850.4133013-8-wesley.cheng@oss.qualcomm.com> <5e9e2824-923c-1328-dd7a-a8b496c44a70@oss.qualcomm.com> From: Wesley Cheng In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: VqTyvlYSm92GfxB-nZT9uiifxrzlRExB X-Authority-Analysis: v=2.4 cv=O4g0fR9W c=1 sm=1 tr=0 ts=68d73114 cx=c_pps a=ULNsgckmlI/WJG3HAyAuOQ==:117 a=ZdW6uxA9NKXbfdqeeS2OGA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=sM_2IyiB1HmcMQZSuvwA:9 a=QEXdDO2ut3YA:10 a=1WsBpfsz9X-RYQiigVTh:22 X-Proofpoint-ORIG-GUID: VqTyvlYSm92GfxB-nZT9uiifxrzlRExB X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTI3MDAwMSBTYWx0ZWRfXzEuXlXCVQnSL xxcM8KeMs2CaxEmvzRp4GsFqug2C340HetBKLASey285epFPC2sBmplOG7zYJviJIniLH84yhIv eBDaS1w27/FMbtgX8wxEB3+JciLNjEHOAYbq+luLVhhOWlZJp95sE23PCnZ9P6OMDf67CM6dkUj 9Fv0lK/UADYtF+IWtEERjE1pgf5UoanVLLFt6HoeGAIbn/uLPaOW35N6DPqMJ0iZU/VOHbiuJRa j9e1b6LS8CpB8esHmNwqR/hQ2nEGVkAuUmRC4eGQ92Yj0+A7PQ1awj08kYGE+4eXv6c1PsxRCgy nVrFccj616IrFfWf9BX9ii7/Ka1/Dhj4TwE/c5gMxVUCisLPwQOYjL9K+h2OeCNXBJ2Zexz3CPH mhMSQUln45bnF44QNcuyv0xBY3GScg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-26_08,2025-09-26_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 spamscore=0 impostorscore=0 bulkscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2509270001 On 9/25/2025 7:11 PM, Dmitry Baryshkov wrote: > On Thu, Sep 25, 2025 at 05:14:30PM -0700, Wesley Cheng wrote: >> >> >> On 9/24/2025 7:54 PM, Dmitry Baryshkov wrote: >>> On Wed, Sep 24, 2025 at 07:28:47PM -0700, Wesley Cheng wrote: >>>> For SuperSpeed USB to work properly, there is a set of HW settings that >>>> need to be programmed into the USB blocks within the QMP PHY. Ensure that >>>> these settings follow the latest settings mentioned in the HW programming >>>> guide. The QMP USB PHY on Glymur is a USB43 based PHY that will have some >>>> new ways to define certain registers, such as the replacement of TXA/RXA >>>> and TXB/RXB register sets. This was replaced with the LALB register set. >>>> >>>> There are also some PHY init updates to modify the PCS MISC register space. >>>> Without these, the QMP PHY PLL locking fails. >>>> >>>> Signed-off-by: Wesley Cheng >>>> --- >>>> drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 311 +++++++++++++++++++++- >>>> drivers/phy/qualcomm/phy-qcom-qmp.h | 4 + >>>> 2 files changed, 314 insertions(+), 1 deletion(-) >>>> >>>> + >>>> +static const struct qmp_phy_init_tbl glymur_usb43dp_pcs_misc_tbl[] = { >>>> + QMP_PHY_INIT_CFG(QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1, 0x01), >>> >>> Why is this V4 all of sudden? >>> >> >> Hi Dmitry, >> >> Will fix.. >> >>>> +}; >>>> + >>>> +static const struct qmp_phy_init_tbl glymur_usb43dp_pcs_tbl[] = { >>>> + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG1, 0xc4), >>>> + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG2, 0x89), >>>> + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG3, 0x20), >>>> + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_LOCK_DETECT_CONFIG6, 0x13), >>>> + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_REFGEN_REQ_CONFIG1, 0x21), >>>> + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_RX_SIGDET_LVL, 0x55), >>>> + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), >>>> + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), >>>> + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_TSYNC_RSYNC_TIME, 0xa4), >>>> + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_RX_CONFIG, 0x0a), >>>> + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_TSYNC_DLY_TIME, 0x04), >>>> + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_ALIGN_DETECT_CONFIG1, 0xd4), >>>> + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_ALIGN_DETECT_CONFIG2, 0x30), >>>> + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_PCS_TX_RX_CONFIG, 0x0c), >>>> + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_EQ_CONFIG1, 0x4b), >>>> + QMP_PHY_INIT_CFG(QPHY_V8_USB43_PCS_EQ_CONFIG5, 0x10), >>>> +}; >>>> + >>>> +static const struct qmp_phy_init_tbl glymur_usb43dp_pcs_usb_tbl[] = { >>>> + QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL, 0xf8), >>>> + QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2, 0x07), >>>> +}; >>>> + >>>> @@ -1667,6 +1899,12 @@ static struct qmp_regulator_data qmp_phy_vreg_l[] = { >>>> { .name = "vdda-pll", .enable_load = 36000 }, >>>> }; >>>> +static struct qmp_regulator_data qmp_phy_vreg_refgen[] = { >>>> + { .name = "vdda-phy", .enable_load = 21800 }, >>>> + { .name = "vdda-pll", .enable_load = 36000 }, >>>> + { .name = "refgen", .enable_load = 936 }, >>> >>> Is this a meaningful value? >>> >> >> I need to adjust this value. I just want the load for the regulators to be >> in HPM, and after taking a look, looks like based on the rpmh regulator >> table, I need to be voting 35000. > > Please provide a value from the platform data rather than just the HPM > boundary. > OK, I referenced our power grid for the correct Ipeak for that particular regulator. Will update this number accordingly. Thanks Wesley Cheng >> >> Thanks >> Wesley Cheng >> >>>> +}; >>>> + >>>> static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { >>>> { 0x00, 0x0c, 0x15, 0x1a }, >>>> { 0x02, 0x0e, 0x16, 0xff }, >>> >