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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b79f44597c1sm135442866b.13.2025.12.04.05.48.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Dec 2025 05:48:15 -0800 (PST) Message-ID: <898e5a54-3a79-4fdc-bb51-f1eb6a79dc0e@oss.qualcomm.com> Date: Thu, 4 Dec 2025 14:48:12 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/5] clk: qcom: cmnpll: Add IPQ5332 SoC support To: Jie Luo , Bjorn Andersson , Michael Turquette , Stephen Boyd , Luo Jie , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_pavir@quicinc.com, quic_suruchia@quicinc.com References: <20251128-qcom_ipq5332_cmnpll-v1-0-55127ba85613@oss.qualcomm.com> <20251128-qcom_ipq5332_cmnpll-v1-3-55127ba85613@oss.qualcomm.com> <6e12f446-7792-44da-9e06-99729c3b066d@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: YLYRFLwYtwI31OqTZFquisvRnzdg5Mag X-Proofpoint-ORIG-GUID: YLYRFLwYtwI31OqTZFquisvRnzdg5Mag X-Authority-Analysis: v=2.4 cv=esHSD4pX c=1 sm=1 tr=0 ts=69319120 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=en7o4u-K8g9yutxgwuQA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA0MDExMiBTYWx0ZWRfX1A4RTnHLujjT Aqa9RWasIn7jofF3Mc3I2uu5lS7kIJfzSzvreIDhp6b1jZD/vQkTOpoScdRqArzZsqTjZ1lEs8c hAGPIFa0JlW6PpJYdb90vvN2VzbxzE1kVVQQ25Ka+vIGGMfe8G0+adV72F7RMik0CCnFfMDSVca SrilLx6852icQ6myhEawpzxE7sb1IlkZ2/Dw0YGL7OGVoSvE01YLtaUU8SwRWe+fsnzAqOPSwBc VMVIJdjBY2EEtNCmBLVPqkbe4V+SjvtL2vXNMk5Q0xbYCiB22Ov+LsLQolQOEALoYd/tTdS3Pmi I3B+6QBHah4+591lRtfnIJIt0Rl8nGdoUz8EADjNucEPN4XLIggyNlaYBmk/MVtR3hUpQAytdm5 06mQ0kWarIQDznNsG4MVPV4ts7ERzg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-04_03,2025-12-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 adultscore=0 malwarescore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512040112 On 12/4/25 9:09 AM, Jie Luo wrote: > > > On 12/1/2025 9:52 PM, Konrad Dybcio wrote: >> On 11/28/25 9:40 AM, Luo Jie wrote: >>> The CMN PLL in IPQ5332 SoC produces different output clocks when compared >>> to IPQ9574. While most clock outputs match IPQ9574, the ethernet PHY/switch >>> (50 Mhz) and PPE clocks (200 Mhz) in IPQ5332 are different. >>> >>> Add IPQ5332-specific clock definitions and of_device_id entry. >>> >>> Signed-off-by: Luo Jie >>> --- >> >> [...] >> >>> +static const struct cmn_pll_fixed_output_clk ipq5332_output_clks[] = { >>> + CLK_PLL_OUTPUT(IPQ5332_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), >>> + CLK_PLL_OUTPUT(IPQ5332_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), >>> + CLK_PLL_OUTPUT(IPQ5332_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL), >>> + CLK_PLL_OUTPUT(IPQ5332_NSS_300MHZ_CLK, "nss-300mhz", 300000000UL), >>> + CLK_PLL_OUTPUT(IPQ5332_PPE_200MHZ_CLK, "ppe-200mhz", 200000000UL), >>> + CLK_PLL_OUTPUT(IPQ5332_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL), >> >> I can't really find the source for most of these, but I see that there's both >> a 200 and a 300 MHz output to NSS >> >> Konrad > > Both IPQ5332_XO_24MHZ_CLK and IPQ5332_SLEEP_32KHZ_CLK are intended to be > used as the input clocks to the GCC block. IPQ5332_PCS_31P25MHZ_CLK > provides the reference clock for the Ethernet PCS, and > IPQ5332_ETH_50MHZ_CLK is the source clock for the PCS PLL on IPQ5332. > On this platform the Ethernet clocking path is: > CMN PLL ETH 50 MHz output → PCS PLL (divider + gate) → attached PHY or > switch. What about that 200 MHz NSS output? Is it just renamed to PPE? Konrad