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[75.80.180.230]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-28e8d1d5680sm15167845ad.96.2025.10.02.00.14.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Oct 2025 00:14:39 -0700 (PDT) Message-ID: <8996bd96-0660-70ba-63f4-51111219d146@oss.qualcomm.com> Date: Thu, 2 Oct 2025 00:14:37 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v4 07/10] phy: qualcomm: qmp-combo: Update QMP PHY with Glymur settings Content-Language: en-US To: Dmitry Baryshkov Cc: krzk+dt@kernel.org, conor+dt@kernel.org, konrad.dybcio@oss.qualcomm.com, kishon@kernel.org, vkoul@kernel.org, gregkh@linuxfoundation.org, robh@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20251001220534.3166401-1-wesley.cheng@oss.qualcomm.com> <20251001220534.3166401-8-wesley.cheng@oss.qualcomm.com> From: Wesley Cheng In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=RZKdyltv c=1 sm=1 tr=0 ts=68de2662 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=agQD+r7xwyS+FYqxhQjztw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=JfrnYn6hAAAA:8 a=EUspDBNiAAAA:8 a=INxguLwuHvTa_v7rZvUA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=1CNFftbPRP8L7MoqJWF3:22 X-Proofpoint-GUID: CKEY8y0ysba8JWe8QjYUI8s2dNsoI_LR X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTI3MDAzMyBTYWx0ZWRfX1UJ4LaQHjCBt t7tSpWlmbub154zc8MDKuiTFX28//iw5QVqyo6hmWnnZrkq0gR+zK5cEvIpXEaQ/t2AgZydGDsI GCUMKZ7WypkJdZ+a1T8L+r/yZfRH15lWUSuq4ecC1vf3kQVr9+J4DQXOM3jIfqJ1JwSe3MyYYgK Ac5eo+EfR1as6fEALaxiWpVJn48hvWZYCCCebl1MJlknO1lHdeH3JeU1X/jcnpSV3/IQFP2pMeW 6qms/hfcp4EgWCxW8irGnLfUmYUWxxjX4NN+90BjARgZbc6Z1XhUaWp2EswaCJGko8Bsy3gISYO ucf9RWrJuPPliSEUo8Hy72rGc2cF7uw14qqkuXFdVD3sGkrERTYwfSFcbopoIU4EY+YVkNZ/PRx P/Re0jlWUql1kqOGFz10x9jM9f74Sg== X-Proofpoint-ORIG-GUID: CKEY8y0ysba8JWe8QjYUI8s2dNsoI_LR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-02_03,2025-09-29_04,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 priorityscore=1501 adultscore=0 phishscore=0 impostorscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2509270033 On 10/1/2025 5:58 PM, Dmitry Baryshkov wrote: > On Wed, Oct 01, 2025 at 03:05:31PM -0700, Wesley Cheng wrote: >> For SuperSpeed USB to work properly, there is a set of HW settings that >> need to be programmed into the USB blocks within the QMP PHY. Ensure that >> these settings follow the latest settings mentioned in the HW programming >> guide. The QMP USB PHY on Glymur is a USB43 based PHY that will have some >> new ways to define certain registers, such as the replacement of TXA/RXA >> and TXB/RXB register sets. This was replaced with the LALB register set. >> >> There are also some PHY init updates to modify the PCS MISC register space. >> Without these, the QMP PHY PLL locking fails. >> >> Signed-off-by: Wesley Cheng >> --- >> drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 312 ++++++++- >> .../phy/qualcomm/phy-qcom-qmp-pcs-aon-v8.h | 17 + >> .../phy/qualcomm/phy-qcom-qmp-pcs-misc-v8.h | 12 + >> .../qualcomm/phy-qcom-qmp-qserdes-lalb-v8.h | 639 ++++++++++++++++++ >> .../phy/qualcomm/phy-qcom-qmp-usb43-pcs-v8.h | 33 + >> .../phy-qcom-qmp-usb43-qserdes-com-v8.h | 224 ++++++ >> drivers/phy/qualcomm/phy-qcom-qmp.h | 4 + >> 7 files changed, 1240 insertions(+), 1 deletion(-) >> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v8.h >> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v8.h >> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-lalb-v8.h >> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-usb43-pcs-v8.h >> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-usb43-qserdes-com-v8.h >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h >> index da2a7ad2cdcc..7211c71fe68c 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-qmp.h >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h >> @@ -32,7 +32,9 @@ >> #include "phy-qcom-qmp-qserdes-txrx-v7.h" >> >> #include "phy-qcom-qmp-qserdes-com-v8.h" >> +#include "phy-qcom-qmp-usb43-qserdes-com-v8.h" >> #include "phy-qcom-qmp-qserdes-txrx-v8.h" >> +#include "phy-qcom-qmp-qserdes-lalb-v8.h" >> >> #include "phy-qcom-qmp-qserdes-pll.h" >> >> @@ -60,6 +62,8 @@ >> >> #include "phy-qcom-qmp-pcs-v8_50.h" >> >> +#include "phy-qcom-qmp-usb43-pcs-v8.h" > > Let's not include USB-specific header into the generic header. Hi Dmitry, This is actually referring to the QMP PCS register set for the USB43 based PHYs. Even though it is a QMP PHY v8 (ie phy-qcom-qmp-pcs-v8), there are some offset differences between the existing one and the one being added. In that case, should we still have it in the USB specific QMP combo driver? I guess it might make sense to have it there, as technically the usb43 based phy is only really going to be there for USB4 capable cores, and I don't think there's much that is common between usb43 and other HW that utilize/share the QMP PHY. Thanks Wesley Cheng > > With that fixed: > > > Reviewed-by: Dmitry Baryshkov > > > >> + >> /* QPHY_SW_RESET bit */ >> #define SW_RESET BIT(0) >> /* QPHY_POWER_DOWN_CONTROL */ >> >> -- >> linux-phy mailing list >> linux-phy@lists.infradead.org >> https://lists.infradead.org/mailman/listinfo/linux-phy >