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Thu, 06 Aug 2026 03:47:25 -0700 (PDT) X-Received: by 2002:a05:6a00:3c84:b0:845:e9f8:67de with SMTP id d2e1a72fcca58-84f2e0555a6mr14758664b3a.27.1786013245412; Thu, 06 Aug 2026 03:47:25 -0700 (PDT) Received: from [10.218.10.148] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84f453bb24csm1138822b3a.24.2026.08.06.03.47.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Aug 2026 03:47:24 -0700 (PDT) Message-ID: <89c7178e-dab2-4b2a-8d8c-c91363b7280d@oss.qualcomm.com> Date: Thu, 6 Aug 2026 16:17:19 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] iommu/arm-smmu: Use pm_runtime in fault handlers To: Pranjal Shrivastava Cc: Will Deacon , Robin Murphy , Joerg Roedel , Rob Clark , Connor Abbott , linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Akhil P Oommen , Pratyush Brahma References: <20260630-smmu-rpm-v3-1-f69874a580fa@oss.qualcomm.com> Content-Language: en-US From: Prakash Gupta In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwODA2MDA4NSBTYWx0ZWRfX1tQIPnAKtRFq CABO9dI5OOO2MQhgjf5PGHf2GzfQIbxNNqmz1BOQNDDoKO2jPVXUx8Y1rH/43+M1IHk3MOGzIZz xGYbZhLI/gooTJFra3c4QrRs02VkxyE= X-Authority-Analysis: v=2.4 cv=RPeD2Yi+ c=1 sm=1 tr=0 ts=6a746641 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=1XWaLZrsAAAA:8 a=k4Bztf7HfYMb5pBHrIQA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-GUID: TvXGgrOCvl6KrJFseEQ9pAM2FmuZsVFb X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA2MDA4NSBTYWx0ZWRfX7boFkBKv/Wl3 HgBdssEcvQuo6yviqaAt4RQ54TgVqVRMmIkWsrQafTWNvR5ZoyEqiMtngzOjxS6jc1tgFMHHQ0z u6di+6z6jtjoY83UD2Ukik6emAQq7Kv6huerOGxUDm1Qj/G6BC91WtY8jVmn+A+IRZ+M21dfe1e Tqsckrn24gUaSL5DCMY+ZGTsX8h6uKv0wkv2AW91znQ8qKKx34xk1EB4UNjY4UenyGAZ3XTx4/v vEMKkPfjrfsqxKKxjCDYEijtvrbBzL64d5aPKLTNR00gacpyVz4JeKzhPdQCj0uUMqJXRmSAnz0 Ghc69Evm+IWj4yV2h4KR9kWvfpKq46sh2IIVtGz0/lbvbbrsDN2iM8+xAlQBaga0pxxScYBjNul /GaYf8x6Zdb3/jTXYA3eYPVPjdssocuxTTMX1d8G0jJzcqIdzJLZARUwrH54Bn9Sq21XklLjU4E 29b8NFan0UfxSdNV39g== X-Proofpoint-ORIG-GUID: TvXGgrOCvl6KrJFseEQ9pAM2FmuZsVFb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-05_06,2026-08-05_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 spamscore=0 priorityscore=1501 impostorscore=0 adultscore=0 phishscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608060085 On 8/3/2026 5:04 PM, Pranjal Shrivastava wrote: > On Tue, Jun 30, 2026 at 02:32:46PM +0530, Prakash Gupta wrote: > > Hi Prakash, > > On a second thought, I'd like to discuss one more thing > >> Commit d4a44f0750bb ("iommu/arm-smmu: Invoke pm_runtime across the driver") >> enabled pm_runtime for the arm-smmu device. On systems where the SMMU >> sits in a power domain, all register accesses must be done while the >> device is runtime active to avoid unclocked register reads and >> potential NoC errors. >> >> So far, this has not been an issue for most SMMU clients because >> stall-on-fault is enabled by default. While a translation fault is >> being handled, the SMMU stalls further translations for that context >> bank, so the fault handler would not race with a powered-down SMMU. >> >> Adreno SMMU now disables stall-on-fault in the presence of fault >> storms to avoid saturating SMMU resources and hanging the GMU. With >> stall-on-fault disabled, the SMMU can generate faults while its power >> domain may no longer be enabled, which makes unclocked accesses to >> fault-status registers in the SMMU fault handlers possible. >> >> Guard the context and global fault handlers with >> arm_smmu_rpm_get_if_active() and arm_smmu_rpm_put() so that all SMMU >> fault register accesses are done with the SMMU powered. If the SMMU is >> not runtime active, the fault can be safely ignored as >> arm_smmu_device_reset() clears fault registers on resume. >> >> Additionally, disable fault reporting in arm_smmu_runtime_suspend() >> before powering down. pm_runtime_get_if_active() returns 0 during >> RPM_SUSPENDING, so without this, level-triggered fault interrupts would >> cause an interrupt storm while the device is being suspended. >> arm_smmu_device_reset() re-enables fault reporting on resume. >> >> Fixes: b13044092c1e ("drm/msm: Temporarily disable stall-on-fault after a page fault") >> Co-developed-by: Pratyush Brahma >> Signed-off-by: Pratyush Brahma >> Signed-off-by: Prakash Gupta >> @@ -2306,6 +2329,25 @@ static int __maybe_unused arm_smmu_runtime_resume(struct device *dev) > > [...] > > I believe, there is a small race condition in the suspend path that can > lead to unclocked register access crashes. (Something similar to what > I've attempted to handle in arm-smmu-v3 [1]) > > In arm_smmu_runtime_suspend(), we disable interrupt reporting in sCR0 and > SCTLR, and then immediately call clk_bulk_disable(). This disables the > interrupt generation but what about the interrupt handlers running > *during* suspend? I believe we could have this race: > > CPU 0 (Suspend Context) CPU 1 (Interrupt/ISR Context) > ----------------------- ----------------------------- > 1. arm_smmu_context_fault() starts. > 2. rpm_get_if_active() returns 1. > (Clocks are ON) > 3. arm_smmu_runtime_suspend() > - Clears CFIE/GFIE in registers > (stops new IRQs from firing) > 4. clk_bulk_disable() > (Clocks are CUT) > 5. Attempts MMIO access (e.g, to > clear CB_FSR or CB_RESUME). > --> [CRASH] Unclocked MMIO access > > I believe similar to arm-smmu-v3 [1], we must call synchronize_irq() > on context interrupts after disabling them in the SCTLR but before > we cut the clocks. This forces CPU 0's suspend thread to sleep and wait > for any active ISRs to safely drain while the SMMU still has clocks. > > We can simply add this loop to arm_smmu_runtime_suspend(): > >> static int __maybe_unused arm_smmu_runtime_suspend(struct device *dev) >> { >> struct arm_smmu_device *smmu = dev_get_drvdata(dev); >> + int i; >> + u32 reg; >> + >> + /* >> + * Disable fault reporting before powering down to prevent unclocked >> + * register accesses in the fault handlers if an interrupt races with >> + * the suspend callback (e.g. device in RPM_SUSPENDING state). >> + * arm_smmu_device_reset() re-enables fault reporting on resume. >> + */ >> + reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sCR0); >> + reg &= ~(ARM_SMMU_sCR0_GFRE | ARM_SMMU_sCR0_GFIE | >> + ARM_SMMU_sCR0_GCFGFRE | ARM_SMMU_sCR0_GCFGFIE); >> + arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, reg); >> + >> + for (i = 0; i < smmu->num_context_banks; i++) { >> + reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_SCTLR); >> + reg &= ~(ARM_SMMU_SCTLR_CFIE | ARM_SMMU_SCTLR_CFRE); >> + arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_SCTLR, reg); >> + } > > for (i = 0; i < smmu->num_context_irqs; i++) > synchronize_irq(smmu->irqs[i]); > >> >> clk_bulk_disable(smmu->num_clks, smmu->clks); >> > > Since we're disabling those interrupts and fixing concurrency, > this seems like the perfect opportunity to add the sync_irq too.. > > What do you think? > > With that loop added: > > Reviewed-by: Pranjal Shrivastava > Thanks Pranjal for review feedback. I have addressed the comments in v4. Thanks, Prakash /com