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Mon, 06 Apr 2026 01:25:56 -0700 (PDT) X-Received: by 2002:a05:6a00:c92:b0:82c:d6d3:3197 with SMTP id d2e1a72fcca58-82d0daadb73mr12018025b3a.23.1775463956288; Mon, 06 Apr 2026 01:25:56 -0700 (PDT) Received: from [10.217.223.121] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82cf9b5fb22sm16753198b3a.26.2026.04.06.01.25.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Apr 2026 01:25:55 -0700 (PDT) Message-ID: <89d95bae-01d3-44b8-b3b6-5e70074d272e@oss.qualcomm.com> Date: Mon, 6 Apr 2026 13:55:46 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 01/11] dt-bindings: crypto: qcom,ice: Fix missing power-domain and iface clk From: Harshal Dev To: Kuldeep Singh , Herbert Xu , "David S. Miller" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Manivannan Sadhasivam , cros-qcom-dts-watchers@chromium.org, Eric Biggers , Dmitry Baryshkov , Jingyi Wang , Tengfei Fan , Bartosz Golaszewski , David Wronek , Luca Weiss , Neil Armstrong , Melody Olvera , Alexander Koskovich Cc: Brian Masney , Neeraj Soni , Gaurav Kashyap , linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Krzysztof Kozlowski References: <20260323-qcom_ice_power_and_clk_vote-v4-0-e36044bbdfe9@oss.qualcomm.com> <20260323-qcom_ice_power_and_clk_vote-v4-1-e36044bbdfe9@oss.qualcomm.com> <873e8ad2-50cd-4c09-9a51-20ad745fe8dc@oss.qualcomm.com> <2b71dd68-ff35-411e-905d-3ffa2ea3efe4@oss.qualcomm.com> Content-Language: en-US In-Reply-To: <2b71dd68-ff35-411e-905d-3ffa2ea3efe4@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA2MDA4MSBTYWx0ZWRfX41nxYaEd5+mB 0QOOunKhsfNRsmehWvNtB2Yv6ZKVGaJeJepOlHv/LIHlYCO2oiMmRiSjxdGEF6IeX1xCKPhPjRO k7pUYpNHKU+IrXfAvzPpWzBT3t+nRZKCvjjNTLC/JVgDW1eXuzpgMFdkHTIYNT+zVhUeoej5XgN 49uge1S2lRmd1Q1T2WsJUJ6qkVydhOraaTbKaJsRFVIBos9Epo3JNeOoKSCCqfPAGBUZwQ5V26F 9t5UoaCluIK6UINjJXNoy4VOKBYasQsF/uexHdgArvYF8DuveimjQRcEUbqBAxdSK22eMSKQUEn UlN+5DB2/V2GRRcbhjYRu/hiaiA08DEVur7S7C00dOEsVt2a8m86wwjpx7ImIIKHQ0852czk1v8 Mwz0Ig3trJqouBgkFJX0KHhKbkf3lj7EQzWq1IuAvzYmRyw+QyTGvLldHDVkLtNcgEuIR39ErEr PtasBABKtOO8HPG7EGA== X-Proofpoint-GUID: nAbxYvj8rwg7mcdk3ridxHtwmcEmEFa5 X-Authority-Analysis: v=2.4 cv=RJ2+3oi+ c=1 sm=1 tr=0 ts=69d36e15 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=P-IC7800AAAA:8 a=EUspDBNiAAAA:8 a=qoNIJ1LOUDDmZ2oDbzIA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 a=d3PnA9EDa4IxuAV0gXij:22 X-Proofpoint-ORIG-GUID: nAbxYvj8rwg7mcdk3ridxHtwmcEmEFa5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-06_02,2026-04-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 adultscore=0 clxscore=1015 spamscore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604060081 Hi Krzysztof, May I request your review on this commit once again. Hopefully I have resolved the issues pointed out in the previous version of this commit. Thank you very much, Harshal On 3/31/2026 3:10 PM, Harshal Dev wrote: > Hi Kuldeep, > > On 3/24/2026 4:16 PM, Kuldeep Singh wrote: >> >> On 3/23/2026 2:47 PM, Harshal Dev wrote: >>> The DT bindings for inline-crypto engine do not specify the UFS_PHY_GDSC >>> power-domain and iface clock. Without enabling the iface clock and the >>> associated power-domain the ICE hardware cannot function correctly and >>> leads to unclocked hardware accesses being observed during probe. >>> >>> Fix the DT bindings for inline-crypto engine to require the UFS_PHY_GDSC >>> power-domain and iface clock for new devices (Eliza and Milos) introduced >>> in the current release (7.0) with yet-to-stabilize ABI, while preserving >>> backward compatibility for older devices. >>> >>> Fixes: 618195a7ac3df ("dt-bindings: crypto: qcom,inline-crypto-engine: Document the Eliza ICE") >>> Fixes: 85faec1e85555 ("dt-bindings: crypto: qcom,inline-crypto-engine: document the Milos ICE") >>> Signed-off-by: Harshal Dev >>> --- >>> .../bindings/crypto/qcom,inline-crypto-engine.yaml | 35 +++++++++++++++++++++- >>> 1 file changed, 34 insertions(+), 1 deletion(-) >>> >>> diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml >>> index 876bf90ed96e..ccb6b8dd8e11 100644 >>> --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml >>> +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml >>> @@ -30,6 +30,16 @@ properties: >>> maxItems: 1 >>> >>> clocks: >>> + minItems: 1 >>> + maxItems: 2 >>> + >>> + clock-names: >>> + minItems: 1 >>> + items: >>> + - const: core >>> + - const: iface >>> + >>> + power-domains: >>> maxItems: 1 >>> >>> operating-points-v2: true >>> @@ -44,6 +54,25 @@ required: >>> >>> additionalProperties: false >>> >>> +allOf: >>> + - if: >>> + properties: >>> + compatible: >>> + contains: >>> + enum: >>> + - qcom,eliza-inline-crypto-engine >>> + - qcom,milos-inline-crypto-engine >>> + >>> + then: >>> + required: >>> + - power-domains >>> + - clock-names >>> + properties: >>> + clocks: >>> + minItems: 2 >>> + clock-names: >>> + minItems: 2 >>> + >> >> Hi Krzysztof, >> >> As motive here is to enforce 2 clocks for upcoming targets and keep >> minItems as 1 for already merged ones for ensuring backward >> compatibility. Can we do like below? >> >> allOf: >> - if: >> not: >> properties: >> compatible: >> contains: >> enum: >> - qcom,kaanapali-inline-crypto-engine >> - qcom,qcs8300-inline-crypto-engine >> - qcom,sa8775p-inline-crypto-engine >> - qcom,sc7180-inline-crypto-engine >> - qcom,sc7280-inline-crypto-engine >> - qcom,sm8450-inline-crypto-engine >> - qcom,sm8550-inline-crypto-engine >> - qcom,sm8650-inline-crypto-engine >> - qcom,sm8750-inline-crypto-engine >> >> then: >> required: >> - power-domains >> - clock-names >> properties: >> clocks: >> minItems: 2 >> clock-names: >> minItems: 2 >> >> This will ensure for every new target addition, default clock count is >> enforced as 2 default. >> Please share your thoughts as well. >> > > I don't really have any particular objections to this proposal, but I can > see that other bindings where the need for an additional clock was realized > later on use a similar pattern as this patchset does: > https://elixir.bootlin.com/linux/v7.0-rc2/source/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml > > I'll wait for Krzysztof to take a final call on this. > > Regards, > Harshal >