From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E196EC4332F for ; Wed, 13 Dec 2023 08:16:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231896AbjLMIQj (ORCPT ); Wed, 13 Dec 2023 03:16:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231226AbjLMIQg (ORCPT ); Wed, 13 Dec 2023 03:16:36 -0500 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D1239F; Wed, 13 Dec 2023 00:16:43 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3BD8GXxT059954; Wed, 13 Dec 2023 02:16:33 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1702455393; bh=FStV+DQOwLOG+FKKRELWFahKxJNKTxkxhmIijEdUO3M=; h=Date:CC:Subject:To:References:From:In-Reply-To; b=v+kMrcXy8lzWgCOI60Q8ItTyzhNVJoJZ3z+KuZFNjI9Bvhj/XMo6S1yXenbJT14TF CuZor7IQ8Zh1RZU2H+SnZS7hjMIuW1EWCFPnRC+2Xi2asPD5ux9an9I3SV4uxcOv3R rQ9KnS/2G2KaPLtVzW6XXr0G+3FeHSao5uztB7V4= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3BD8GXej119101 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 13 Dec 2023 02:16:33 -0600 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 13 Dec 2023 02:16:33 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 13 Dec 2023 02:16:33 -0600 Received: from [172.24.227.9] (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3BD8GTW1040313; Wed, 13 Dec 2023 02:16:30 -0600 Message-ID: <89ed9033-7fbd-4a48-9a83-0a0b3b208e3d@ti.com> Date: Wed, 13 Dec 2023 13:46:28 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird CC: , , , , , , , , , , , Subject: Re: [PATCH] arm64: dts: ti: k3-am654-icssg2: Enable PHY interrupts for ICSSG2 Content-Language: en-US To: Nishanth Menon References: <20231120063159.539306-1-s-vadapalli@ti.com> <20231204132103.ikkxjz3yxz3ynq6s@demystify> From: Siddharth Vadapalli In-Reply-To: <20231204132103.ikkxjz3yxz3ynq6s@demystify> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello Nishanth, Thank you for reviewing the patch. I have addressed your feedback in the v2 patch at: https://lore.kernel.org/r/20231213080216.1710730-1-s-vadapalli@ti.com/ On 04/12/23 18:51, Nishanth Menon wrote: > On 12:01-20231120, Siddharth Vadapalli wrote: >> Enable interrupt mode of operation of the DP83867 Ethernet PHY which is >> used by ICSSG2. The DP83867 PHY driver already supports interrupt handling >> for interrupts generated by the PHY. Thus, add the necessary device-tree >> support to enable it. >> >> Since the GPIO1_87 line is muxed with EXT_REFCLK1 and SYNC1_OUT, update >> the pinmux to select GPIO1_87 for routing the interrupt. >> >> Signed-off-by: Siddharth Vadapalli >> --- >> >> This patch is based on linux-next tagged next-20231120. >> >> Regards, >> Siddharth. >> >> arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso | 17 +++++++++++++++-- >> 1 file changed, 15 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso b/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso >> index ec8cf20ca3ac..9f723592d0f4 100644 >> --- a/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso >> +++ b/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso >> @@ -124,21 +124,34 @@ AM65X_IOPAD(0x0088, PIN_INPUT, 2) /* (AG17) PRG2_PRU0_GPO4.PRG2_RGMII1_RX_CTL */ >> }; >> }; >> >> +&main_pmx1 { >> + /* Select GPIO1_87 for ICSSG2 PHY interrupt */ >> + icssg2_phy_irq_pins_default: icssg2-phy-irq-default-pins { >> + pinctrl-single,pins = < >> + AM65X_IOPAD(0x0014, PIN_INPUT, 7) /* (A22) EXT_REFCLK1.GPIO1_87 */ >> + >; >> + }; >> +}; >> + >> &icssg2_mdio { >> status = "okay"; >> - pinctrl-names = "default"; >> - pinctrl-0 = <&icssg2_mdio_pins_default>; >> + pinctrl-names = "default", "icssg2-phy-irq"; >> + pinctrl-0 = <&icssg2_mdio_pins_default>, <&icssg2_phy_irq_pins_default>; > > why should the pins be part of mdio pinctrl instead of phy? > >> #address-cells = <1>; >> #size-cells = <0>; >> >> icssg2_phy0: ethernet-phy@0 { >> reg = <0>; >> + interrupt-parent = <&main_gpio1>; >> + interrupts = <87 0x2>; >> ti,rx-internal-delay = ; >> ti,fifo-depth = ; >> }; >> >> icssg2_phy1: ethernet-phy@3 { >> reg = <3>; >> + interrupt-parent = <&main_gpio1>; >> + interrupts = <87 0x2>; > > Shouldn't you be using macros for interrupt level like IRQ_TYPE_EDGE_FALLING? > >> ti,rx-internal-delay = ; >> ti,fifo-depth = ; >> }; >> -- >> 2.34.1 >> > -- Regards, Siddharth.