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Thu, 11 Jun 2026 09:22:10 -0700 (PDT) X-Received: by 2002:a17:903:1984:b0:2c1:5135:39f3 with SMTP id d9443c01a7336-2c2f0639a6dmr44759545ad.11.1781194929759; Thu, 11 Jun 2026 09:22:09 -0700 (PDT) Received: from [192.168.1.8] ([122.164.81.0]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c164fa3a5fsm296310835ad.36.2026.06.11.09.22.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 Jun 2026 09:22:09 -0700 (PDT) Message-ID: <8a0e9314-0c97-48c8-be95-986c7e6fe641@oss.qualcomm.com> Date: Thu, 11 Jun 2026 21:52:04 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/2] Add support for the QMP PCIe PHYs in Qualcomm IPQ9650 To: Vinod Koul Cc: Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260602-ipq9650_pcie_phy-v1-0-d8c32a36dbd9@oss.qualcomm.com> Content-Language: en-US From: Kathiravan Thirumoorthy In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: NnWaT8be2qLKQvWnd5dUuuSzeMEyN_z1 X-Proofpoint-GUID: NnWaT8be2qLKQvWnd5dUuuSzeMEyN_z1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjExMDE2NCBTYWx0ZWRfX4VKoFol/PR0E qndu0uZ+lBJxX4clIS8XsSCMtS9WlnLYPb12nz5oSo7sQ/sIwU5iqowEAot5BwsVeY//ggsG0ke iovdo5heWevGPI5IcLdEkcVHm7u4Q/YRp6sPUpXOZDARqWDjx+gHPn/Xr5spMWeNSY2qXbDDyAK OHKjCFy79cMuNA3ry/h/0kEr8E8g8gZo8Dnr468r/+beuuK8PiMKzFQcfwlTDUrHYKMEu5u9XFA I0SS60wcxGgUd/zuV8Y6A0f15GPffkNtAzkWIcLn8x5hy9l1v24g6JRiBkPbXOjZIJsFv7oYRbb Iht0hIgj4PiP1Tqd5ACqtZ37k4wdI0Bk6nC/VE2mBSOW5SHDT/FFCpuFe5TOV1vMcgneD+iLUdW Zd5eev7/UbaRPLuAwP9CCKWx1guYzHc5z6xhfJcJ25UIG15Wg4DJdy/5A8WR3PBOWfKhmX6XsXl q4FTXBOHlBGtP3QzTvw== X-Proofpoint-Spam-Info: AW1haW4tMjYwNjExMDE2NCBTYWx0ZWRfXzu7E9VqgtFQV crJwnhq4bj9+QH7lQpbylpQJ2FAMuP3S8Ypv+95rb8i6M7HwyZ3KXoGuxIMdzfRhIODXv+GgTIu hxZq738PzEQLC0flxAduMCXKLIgygxI= X-Authority-Analysis: v=2.4 cv=Lf0MLDfi c=1 sm=1 tr=0 ts=6a2ae0b3 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=DVNErGSwdtF8OHn2hLoakQ==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=VwQbUJbxAAAA:8 a=MO7iE5JbH1gLMWvasfoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-11_03,2026-06-11_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 phishscore=0 clxscore=1015 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606110164 On 6/11/2026 4:45 PM, Vinod Koul wrote: > On 02-06-26, 14:40, Kathiravan Thirumoorthy wrote: >> Qualcomm's IPQ9650 SoC has 3 Gen3 dual lane and 2 Gen3 single lane >> controllers with the QMP PHYs. Unlike the PHYs in the other IPQ SoC, >> refgen supply is needed to bringup the PHYs. Both single and dual lane >> shares the same HW init sequence. So reuse the tables. >> >> Document the compatible along with refgen supply and add the phy driver >> support for it. > Please rebase this on phy-next tomorrow. It does not apply for me due to > changes applied ealier today There is a discussion open about the supplies[1]. Once that is clarified, let me re spin. So we can take up this series for v7.3 once that discussion is closed. [1] https://lore.kernel.org/linux-arm-msm/aiqYtowP2DQt7Jw0@vaman/T/#m37a571fac0c77fd00f6379ad9a2414b60431820b >