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Tue, 18 Mar 2025 09:11:32 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEDWxl7Dn7VJ/dGBJeY8Nm/beDoadgREWVQ+bpzZHWe/2JguBoReZYgna/7NMPu2dIQzrTEQA== X-Received: by 2002:a17:903:40cb:b0:224:a74:28cd with SMTP id d9443c01a7336-225e0ab5216mr226833365ad.31.1742314292246; Tue, 18 Mar 2025 09:11:32 -0700 (PDT) Received: from [192.168.29.92] ([49.43.228.40]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-225c6ba6d0asm96645755ad.130.2025.03.18.09.11.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Mar 2025 09:11:31 -0700 (PDT) Message-ID: <8a2bce29-95dc-53b0-0516-25a380d94532@oss.qualcomm.com> Date: Tue, 18 Mar 2025 21:41:23 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v4 02/10] arm64: dts: qcom: qcs6490-rb3gen2: Add TC956x PCIe switch node Content-Language: en-US To: Dmitry Baryshkov Cc: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , chaitanya chundru , Bjorn Andersson , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org, Jingoo Han , Bartosz Golaszewski , quic_vbadigan@quicnic.com, amitk@kernel.org, dmitry.baryshkov@linaro.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, jorge.ramirez@oss.qualcomm.com References: <20250225-qps615_v4_1-v4-0-e08633a7bdf8@oss.qualcomm.com> <20250225-qps615_v4_1-v4-2-e08633a7bdf8@oss.qualcomm.com> From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=QN1oRhLL c=1 sm=1 tr=0 ts=67d99b35 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=gzHQz5DndFXDghOZWxpFUA==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=WTmwj_6TxTBwwd-b0B4A:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 5IyR9DYeWoMPuxPMFBss3SxLZIf6WGjr X-Proofpoint-GUID: 5IyR9DYeWoMPuxPMFBss3SxLZIf6WGjr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-18_07,2025-03-17_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 phishscore=0 spamscore=0 impostorscore=0 suspectscore=0 mlxlogscore=999 priorityscore=1501 lowpriorityscore=0 malwarescore=0 adultscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503180119 On 3/17/2025 4:57 PM, Dmitry Baryshkov wrote: > On Tue, Feb 25, 2025 at 03:03:59PM +0530, Krishna Chaitanya Chundru wrote: >> Add a node for the TC956x PCIe switch, which has three downstream ports. >> Two embedded Ethernet devices are present on one of the downstream ports. >> >> Power to the TC956x is supplied through two LDO regulators, controlled by >> two GPIOs, which are added as fixed regulators. Configure the TC956x >> through I2C. >> >> Signed-off-by: Krishna Chaitanya Chundru >> Reviewed-by: Bjorn Andersson >> Acked-by: Manivannan Sadhasivam >> --- >> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 116 +++++++++++++++++++++++++++ >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- >> 2 files changed, 117 insertions(+), 1 deletion(-) >> >> @@ -735,6 +760,75 @@ &pcie1_phy { >> status = "okay"; >> }; >> >> +&pcie1_port { >> + pcie@0,0 { >> + compatible = "pci1179,0623", "pciclass,0604"; >> + reg = <0x10000 0x0 0x0 0x0 0x0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + >> + device_type = "pci"; >> + ranges; >> + bus-range = <0x2 0xff>; >> + >> + vddc-supply = <&vdd_ntn_0p9>; >> + vdd18-supply = <&vdd_ntn_1p8>; >> + vdd09-supply = <&vdd_ntn_0p9>; >> + vddio1-supply = <&vdd_ntn_1p8>; >> + vddio2-supply = <&vdd_ntn_1p8>; >> + vddio18-supply = <&vdd_ntn_1p8>; >> + >> + i2c-parent = <&i2c0 0x77>; >> + >> + reset-gpios = <&pm8350c_gpios 1 GPIO_ACTIVE_LOW>; >> + > > I think I've responded here, but I'm not sure where the message went: > please add pinctrl entry for this pin. > Do we need to also add pinctrl property for this node and refer the pinctrl entry for this pin? - Krishna Chaitanya.