From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 572B5C7EE32 for ; Tue, 30 May 2023 08:00:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229838AbjE3IAa (ORCPT ); Tue, 30 May 2023 04:00:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229739AbjE3IAZ (ORCPT ); Tue, 30 May 2023 04:00:25 -0400 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A817EDB; Tue, 30 May 2023 01:00:23 -0700 (PDT) Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34U3trF5017624; Tue, 30 May 2023 10:00:02 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=selector1; bh=F6s3aD3XjXvai6aASf5oktFqcXSWfCYGDRUtEZKcHTU=; b=JiwR7fSL+Spg+EPI/ayGRMDGZe+2f1u/NpUH/q7aXfsopV7ie2mDahW8OLSZ3v5vYIUI k8fOovmZEL+hbAyBQpA1pH9rWegcACyQ45cX2idDAWHxICeyJXug0XrbY1ZZsMfuSNgE TK9eAm2/lN4fmY56I5uhvL2/I5LZGBZtDJxlcjbpNs/t6DyRAeiWUJtDGf58LhpR9BLw 3cZ7X69JRBDhP4c0pvWG/CZ/Syhip1f0ajVN4kmKUvSSB69G6J1VjfmD83JMnZJW46Lk sLcLvNCfAFrbjx16omnWL82R96MA8bkBRym024YLXWd08l26HzBDnvHPOtDbo6kUBhZd UA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3quahy634c-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 30 May 2023 10:00:02 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D281B10002A; Tue, 30 May 2023 10:00:00 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id C872C2138F6; Tue, 30 May 2023 10:00:00 +0200 (CEST) Received: from [10.201.21.93] (10.201.21.93) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 30 May 2023 10:00:00 +0200 Message-ID: <8a4f3112-54ed-e0c1-52ee-395a41255163@foss.st.com> Date: Tue, 30 May 2023 09:59:59 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH 7/8] ARM: dts: stm32: adopt generic iio bindings for adc channels on dhcor-drc Content-Language: en-US To: Olivier MOYSAN , Marek Vasut , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin CC: , , , , References: <20230524133918.1439516-1-olivier.moysan@foss.st.com> <20230524133918.1439516-8-olivier.moysan@foss.st.com> <5bb496d0-6dc1-6ba3-6126-6429037ecf5a@foss.st.com> From: Alexandre TORGUE In-Reply-To: <5bb496d0-6dc1-6ba3-6126-6429037ecf5a@foss.st.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.201.21.93] X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-30_05,2023-05-29_02,2023-05-22_02 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Marek, Olivier On 5/24/23 17:39, Olivier MOYSAN wrote: > Hi Marek, > > On 5/24/23 15:54, Marek Vasut wrote: >> On 5/24/23 15:39, Olivier Moysan wrote: >>> Use STM32 ADC generic bindings instead of legacy bindings on >>> DHCOR DRC Compact board. >>> >>> The STM32 ADC specific binding to declare channels has been deprecated, >>> hence adopt the generic IIO channels bindings, instead. >>> The STM32MP151 device tree now exposes internal channels using the >>> generic binding. This makes the change mandatory here to avoid a mixed >>> use of legacy and generic binding, which is not supported by the driver. >>> >>> Signed-off-by: Olivier Moysan >>> --- >>>   .../dts/stm32mp15xx-dhcor-drc-compact.dtsi    | 28 ++++++++++++++++--- >>>   1 file changed, 24 insertions(+), 4 deletions(-) >>> >>> diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi >>> b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi >>> index 39af79dc654c..92d906bfd5d7 100644 >>> --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi >>> +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi >>> @@ -57,15 +57,35 @@ &adc {    /* X11 ADC inputs */ >>>       status = "okay"; >>>       adc1: adc@0 { >> >> >> I sent similar patch recently too: >> >> [PATCH] ARM: dts: stm32: Update to generic ADC channel binding on >> DHSOM systems >> >> But I needed to add #address-cells/#size-cells here and to adc@100, >> otherwise DTB checker was complaining . Did you run DTB check and was >> it OK on your side ? > > The first patch in this serie adds the #address-cells/#size-cells to the >  SoC DT. So, there is no need to add them later in the board DT. > > I can send a v2 with your patch (after removing the cells properties > from the patch). Having all the patches in the same serie, will help > avoiding sequencing problems. > > Do you agree with this ? What is the status of this patch ? Marek, I would prefer to take all ADC updates in this series if you agree. Alex > > BRs > Olivier > >> >>> -        st,adc-channels = <0 1 6>; >>> -        st,min-sample-time-nsecs = <5000>; >>>           status = "okay"; >>> +        channel@0 { >>> +            reg = <0>; >>> +            st,min-sample-time-ns = <5000>; >>> +        }; >>> +        channel@1 { >>> +            reg = <1>; >>> +            st,min-sample-time-ns = <5000>; >>> +        }; >>> +        channel@6 { >>> +            reg = <6>; >>> +            st,min-sample-time-ns = <5000>; >>> +        }; >>>       }; >> >> [...]