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Fri, 03 Jul 2026 02:20:14 -0700 (PDT) X-Received: by 2002:a17:902:d4c8:b0:2c9:bd3b:34f with SMTP id d9443c01a7336-2ca911f344fmr96591945ad.35.1783070414411; Fri, 03 Jul 2026 02:20:14 -0700 (PDT) Received: from [10.217.198.242] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13b41c364d5sm12798365c88.14.2026.07.03.02.20.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 03 Jul 2026 02:20:14 -0700 (PDT) Message-ID: <8a538dd5-ab36-4826-929c-8ad16d652728@oss.qualcomm.com> Date: Fri, 3 Jul 2026 14:50:08 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 5/8] irqchip/qcom-pdc: Configure PDC to pass through mode To: Thomas Gleixner , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, Sneh Mankad References: <20260616-hamoa_pdc_v3-v3-0-4d8e1504ea75@oss.qualcomm.com> <20260616-hamoa_pdc_v3-v3-5-4d8e1504ea75@oss.qualcomm.com> <87echoqd7d.ffs@fw13> Content-Language: en-US From: "Maulik Shah (mkshah)" In-Reply-To: <87echoqd7d.ffs@fw13> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: M_DKDSsNLa92r0_K9ukJX5lBudspsRXx X-Proofpoint-Spam-Info: AW1haW4tMjYwNzAzMDA4OCBTYWx0ZWRfX/e/Lh1YdlUvP ZImsPvXQSaEptZPYpvkEtUQ9qYS08+7a5lmWiDZ57a0wx1zuUsAKUK2o3IJmLnaDDut0hpsyyTk WHaTs+PgmLkuK+dVLOMEzmBm/9WvQUI= X-Authority-Analysis: v=2.4 cv=a6QAM0SF c=1 sm=1 tr=0 ts=6a477ecf cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=VwQbUJbxAAAA:8 a=OtCtuEUk8598TF12AxYA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzAzMDA4OCBTYWx0ZWRfX8H08uCha2ivZ MUxmfaF/u9gWqiTudWSAgukqT1fwaACfdE2hHS4TfMwfQCiapjEAOCggM6/W/S7oiZlJEZ6wcwt ChZbo6lZkatTREcUoaLOIubSY6mSHmWhX+SPXFhIDQyuZWn/BBujHajCZOgSxAlaSDkomr0+NSX maDBr5lK5iaOAaxB51LPc7JF7O0NlRdpZSkhTqV2eqHPCOw5Q+t1J8dC2HctlGdNXf0nYWKJuDw nlOIo30yD2A+WjblVYLtF4KnQ/8k/Xzx3Q6QTf3Zs1NyWz/ggiVJw6jzRlQJSoJK0LWw4vMT2YM KrBjKq2EXWm04M3AAdk4Z9qe6Rt7wfHJgTK6BsW2z4nC4cEX3lz0afXfB9JH3XYuzjif0n0aezS kNKXT+TgfoTWH3PkCGG7EXJ7Hx2YQxFA99K9RBiKzIPwPmdDfG+U8jJuwTV17IaGpC3gz8B3JSc 0YNyHdOmLCkGMmMf2bA== X-Proofpoint-ORIG-GUID: M_DKDSsNLa92r0_K9ukJX5lBudspsRXx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-07-03_02,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 impostorscore=0 phishscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607030088 On 6/30/2026 8:37 PM, Thomas Gleixner wrote: > On Tue, Jun 16 2026 at 14:55, Maulik Shah wrote: >> All PDC irqchip supports pass through mode in which both Direct SPIs and > > All PDC variants support pass .. ?? Yes, It should be all PDC HW variants supports...I will update in v4. > >> GPIO IRQs (as SPIs) are sent to GIC without latching at PDC. >> >> Newer PDCs (v3.0 onwards) also support additional secondary controller mode >> where PDC latches GPIO IRQs and sends to GIC as level type IRQ. Direct SPIs > > latches the GPIO interrupts and sends them to GIC as level type interrupts. Sure, I will update in v4. > >> still works same as pass through mode without latching at PDC even in > > SPIs .. work the same as pass-through mode .... Sure, I will update in v4. > >> secondary controller mode. >> >> All the SoCs so far default uses pass through mode with the exception of > > SoCs ... use pass-through Sure, I will update in v4. > >> x1e. x1e PDC may be set to secondary controller mode for builds on CRD >> boards whereas it may be set to pass through mode for IoT-EVK boards. >> The mode configuration is done in firmware and initially shipped windows >> firmware did not have SCM interface to read or modify the PDC mode. >> Later only write access is opened up for non secure world. > > .. for the non-secure .. > Sure, I will update in v4. >> +/** >> + * qcom_pdc_gic_set_type: Configure PDC for the interrupt >> + * >> + * @d: the interrupt data >> + * @type: the interrupt type > > https://docs.kernel.org/process/maintainer-tip.html#struct-declarations-and-initializers > > I'm sure I pointed you to that document before. Yes, missed this place to follow. I will update in v4. > >> + * >> + * All @type are forwarded as Level type to parent GIC >> + */ >> +static int qcom_pdc_gic_secondary_set_type(struct irq_data *d, unsigned int type) >> +{ >> + enum pdc_irq_config_bits pdc_type; >> + enum pdc_irq_config_bits old_pdc_type; > > Chapter before the above ... I will update in v4. > >> @@ -449,8 +628,13 @@ static int pdc_setup_pin_mapping(struct device *dev, struct device_node *np) >> if (ret) >> return ret; >> >> - for (int i = 0; i < pdc->region[n].cnt; i++) >> - pdc->enable_intr(i + pdc->region[n].pin_base, 0); >> + for (int i = 0; i < pdc->region[n].cnt; i++) { >> + if (pdc_pin_is_gpio(i + pdc->region[n].pin_base) && >> + pdc->mode == PDC_SECONDARY_MODE) >> + pdc->clear_gpio(i + pdc->region[n].pin_base); >> + > > Requires guard(irqsave)(...) > Yes, added in v4 within pdc->enable_intr(). Thanks, Maulik