From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 487D22F4A14; Wed, 3 Sep 2025 11:07:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756897627; cv=none; b=i4ZvslbS5tr3GBsOpVOMjglaGnluhCA3CkIvkKSelLAhBFIQkaoNjJ80nkhDzVhHgApqC43wKq8zDfSsieK84fKZHWlYvnYpcJSBknpTOaJSb6z5A3ZJdS5fvpOLf4n7SMRLhSvSj2H9dVUsLw+E1cGnM98/e1spcZcg+gp7iss= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756897627; c=relaxed/simple; bh=virt440YX1VkOxJaTmEr80xjwMryJlZsQui9kt/izTs=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=mB8w2mAHyR6Dn3NIBx8jXKMOWz1El/VGim/ov/X4U+2KuTDWsDoY2enl2hrQn8MkZraT9VsmR3je6J64L3pWurE+AMGT7c0ZGHKpOm4xtXw9MByI3rXy3ht+M8IDlW4mqSVxKPVXMbfAwqc/OxsjDZFNJgDC3+xFVsSrBD1/1y8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=X8WNaEN/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="X8WNaEN/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2F797C4CEF0; Wed, 3 Sep 2025 11:06:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756897626; bh=virt440YX1VkOxJaTmEr80xjwMryJlZsQui9kt/izTs=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=X8WNaEN/VwOhZmnWe6N6MP7x5vfstlLdgDw2eZrZCeb3sK1BIcrWgrADCpGviGRw8 9eXvp6RGfYqzwQ3VPiDQd1B0QvXzi2heoZ6QyApM39eJFhuewyi6wxiMUciaaG9Gtl ySaWqYLyotZFWePjR8RceMk+5F4IfB4wX7CeIOfoFScC9w4l8RLBt534eUcMHkCOt7 DX47DcrOhsixkweNukJ8QvVSuquvQ0MAr/z2JRSSosFemG4LpXfRE/5tOgHWF6DyYM +s7K/ZK1BTWNET730nOALste8EyPz7s8CKPbsVudE05b7jj44zK/1ERrqX5vQoyh+C V1+KewudYEZXA== Date: Wed, 3 Sep 2025 12:06:55 +0100 From: Mark Brown To: Andy Shevchenko Cc: Bartosz Golaszewski , Andy Shevchenko , Linus Walleij , Bjorn Andersson , Konrad Dybcio , Alexey Klimov , Lorenzo Bianconi , Sean Wang , Matthias Brugger , AngeloGioacchino Del Regno , Paul Cercueil , Kees Cook , Andy Shevchenko , Andrew Morton , David Hildenbrand , Lorenzo Stoakes , "Liam R. Howlett" , Vlastimil Babka , Mike Rapoport , Suren Baghdasaryan , Michal Hocko , Dong Aisheng , Fabio Estevam , Shawn Guo , Jacky Bai , Pengutronix Kernel Team , NXP S32 Linux Team , Sascha Hauer , Tony Lindgren , Haojian Zhuang , Geert Uytterhoeven , Greg Kroah-Hartman , "Rafael J. Wysocki" , Danilo Krummrich , Neil Armstrong , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mm@kvack.org, imx@lists.linux.dev, linux-omap@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Bartosz Golaszewski , Konrad Dybcio Subject: Re: [PATCH v7 16/16] pinctrl: qcom: make the pinmuxing strict Message-ID: <8a54bbbd-2b7a-482f-9ab5-eac83264b1f6@sirena.org.uk> References: <20250902-pinctrl-gpio-pinfuncs-v7-16-bb091daedc52@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="/BwkSBKy/i3w/XmA" Content-Disposition: inline In-Reply-To: X-Cookie: You were s'posed to laugh! --/BwkSBKy/i3w/XmA Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Sep 03, 2025 at 01:53:00PM +0300, Andy Shevchenko wrote: > (Not sure, but SPI DesignWare requires programming SPI native chip selects even > if the GPIO is used for that, this might have also some implications, but here > it's for real 'purely speculative'.) It is very common for SPI controllers to absolutely require setting a chip select in order to do a transfer, when using GPIO chip selects with such controllers the standard practice is to just not mux out the chip select signal from the controller and do everything in software. The IP will be doing it's thing with it's chip select signal but that signal is never actually connected to anything. --/BwkSBKy/i3w/XmA Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAmi4IU4ACgkQJNaLcl1U h9AQfAf/cIyTMUWIKvnzF/bbQpaevTEUa1OBu/7ZBFg8nC5nbLhvhVdYli97003E aKUauEzD22LQFP4msSIUEmLifRDXBb4pRIP4hVwWteB+GakiyOdtVyAxV7uySCKT 95KpISbIE8ooH7RkAXe8N1iYnqwy9VRmdjYa2FdzpLuCPCawD0+YiYWzPPLLVtgA quzmvAfna367i9/zeuRw6JPL7bZOm3lq0EAs4Y/xEDQVXW2aVcW5K8mzJqoBJot+ gjs2B5fH1gVJxjLMx5QO/i7tktneqkpdo3YQhL8m9VKl7/DAuBacjsHoBN7exY4u 23ENTRMf7dNs8GE3wrhuLAFBjmihdw== =ZPrJ -----END PGP SIGNATURE----- --/BwkSBKy/i3w/XmA--