From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EC0B2066C7 for ; Fri, 10 Jan 2025 19:45:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736538360; cv=none; b=umDqqXq6n9VKnEoRe4DX7ar6ld+LGxahAQ8S73/cmP6TvKkM8jdceWmmLuY9mlGx0pXnn57bwKk4cROoZEQOq8tM0vIirQ+ONQDEkqL3fVno1SBVdqgGW/1G+7BtEE1BPA0uIKjYNqDD+OCYGbfEyrnccGcTi1DsqIc0GcNV00I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736538360; c=relaxed/simple; bh=6vVbub2DtlihNEc4alwwLyWZAIE4qSfXROFCLRdtC60=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=gfLiE49NBYCBJnlSoKSf3ICbu1vJeSHxz1jk8eFTnffwc00c0M17a0z7qx2CpV991Kc8hj10r4CE0/aHjhVHR5K75KMNCqs/F5QR939qSBbs/zKOTOJzSA0CqRuTS7NBWVNZla4ewNvCWzbWz0SIeqceC3rgYsv2b76wWAdjiSU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tWKwh-000000006Cj-1VSw; Fri, 10 Jan 2025 14:45:27 -0500 Message-ID: <8a8765c3d4f6154d38e00219cae739245d15cc1e.camel@surriel.com> Subject: Re: [PATCH 11/12] x86/mm: enable AMD translation cache extensions From: Rik van Riel To: Tom Lendacky , x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, nadav.amit@gmail.com, zhengqi.arch@bytedance.com, linux-mm@kvack.org Date: Fri, 10 Jan 2025 14:45:27 -0500 In-Reply-To: <2cf92ecf-cd14-734a-6dd9-bd489321651e@amd.com> References: <20241230175550.4046587-1-riel@surriel.com> <20241230175550.4046587-12-riel@surriel.com> <2cf92ecf-cd14-734a-6dd9-bd489321651e@amd.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.1 (3.54.1-1.fc41) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Sender: riel@surriel.com On Fri, 2025-01-10 at 13:34 -0600, Tom Lendacky wrote: >=20 > > +++ b/arch/x86/kernel/cpu/amd.c > > @@ -1143,6 +1143,14 @@ static void cpu_detect_tlb_amd(struct > > cpuinfo_x86 *c) > > =C2=A0 > > =C2=A0 /* Max number of pages INVLPGB can invalidate in one shot > > */ > > =C2=A0 invlpgb_count_max =3D (edx & 0xffff) + 1; > > + > > + /* If supported, enable translation cache extensions (TCE) > > */ > > + cpuid(0x80000001, &eax, &ebx, &ecx, &edx); > > + if (ecx & BIT(17)) { >=20 > Back to my comment from patch #4, you can put this under the > cpu_feature_enabled() check and just set it. >=20 Ohhh nice, so I can just add a CPUID feature bit for TCE, and then have this? if(cpu_feature_enabled(X86_FEATURE_TCE)) msr_set_bit(MSR_EFER, EFER_TCE); That is much nicer. Is this the right location for that code, or do I need to move it somewhere else to guarantee TCE gets enabled on every CPU? > > + u64 msr =3D native_read_msr(MSR_EFER);; > > + msr |=3D BIT(15); > > + wrmsrl(MSR_EFER, msr); >=20 > msr_set_bit() ? >=20 > Thanks, > Tom >=20 > > + } > > =C2=A0} > > =C2=A0 > > =C2=A0static const struct cpu_dev amd_cpu_dev =3D { > > diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c > > index 454a370494d3..585d0731ca9f 100644 > > --- a/arch/x86/mm/tlb.c > > +++ b/arch/x86/mm/tlb.c > > @@ -477,7 +477,7 @@ static void broadcast_tlb_flush(struct > > flush_tlb_info *info) > > =C2=A0 if (info->stride_shift > PMD_SHIFT) > > =C2=A0 maxnr =3D 1; > > =C2=A0 > > - if (info->end =3D=3D TLB_FLUSH_ALL) { > > + if (info->end =3D=3D TLB_FLUSH_ALL || info->freed_tables) { > > =C2=A0 invlpgb_flush_single_pcid(kern_pcid(asid)); > > =C2=A0 /* Do any CPUs supporting INVLPGB need PTI? */ > > =C2=A0 if (static_cpu_has(X86_FEATURE_PTI)) > > @@ -1110,7 +1110,7 @@ static void flush_tlb_func(void *info) > > =C2=A0 * > > =C2=A0 * The only question is whether to do a full or partial > > flush. > > =C2=A0 * > > - * We do a partial flush if requested and two extra > > conditions > > + * We do a partial flush if requested and three extra > > conditions > > =C2=A0 * are met: > > =C2=A0 * > > =C2=A0 * 1. f->new_tlb_gen =3D=3D local_tlb_gen + 1.=C2=A0 We have an > > invariant that > > @@ -1137,10 +1137,14 @@ static void flush_tlb_func(void *info) > > =C2=A0 *=C2=A0=C2=A0=C2=A0 date.=C2=A0 By doing a full flush instead, = we can > > increase > > =C2=A0 *=C2=A0=C2=A0=C2=A0 local_tlb_gen all the way to mm_tlb_gen and= we can > > probably > > =C2=A0 *=C2=A0=C2=A0=C2=A0 avoid another flush in the very near future= . > > + * > > + * 3. No page tables were freed. If page tables were > > freed, a full > > + *=C2=A0=C2=A0=C2=A0 flush ensures intermediate translations in the T= LB > > get flushed. > > =C2=A0 */ > > =C2=A0 if (f->end !=3D TLB_FLUSH_ALL && > > =C2=A0 =C2=A0=C2=A0=C2=A0 f->new_tlb_gen =3D=3D local_tlb_gen + 1 && > > - =C2=A0=C2=A0=C2=A0 f->new_tlb_gen =3D=3D mm_tlb_gen) { > > + =C2=A0=C2=A0=C2=A0 f->new_tlb_gen =3D=3D mm_tlb_gen && > > + =C2=A0=C2=A0=C2=A0 !f->freed_tables) { > > =C2=A0 /* Partial flush */ > > =C2=A0 unsigned long addr =3D f->start; > > =C2=A0 >=20 --=20 All Rights Reversed.