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Wed, 18 Jun 2025 01:28:13 -0700 (PDT) Message-ID: <8a986ebb-5c25-46d9-8a2f-7c0ad7702c15@linaro.org> Date: Wed, 18 Jun 2025 10:28:10 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 08/17] drm/msm/dsi/phy: Fix reading zero as PLL rates when unprepared To: Dmitry Baryshkov Cc: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Clark , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Abel Vesa , Srinivas Kandagatla References: <20250610-b4-sm8750-display-v6-0-ee633e3ddbff@linaro.org> <20250610-b4-sm8750-display-v6-8-ee633e3ddbff@linaro.org> <738a889d-9bd5-40c3-a8f5-f76fcde512f4@oss.qualcomm.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzysztof.kozlowski@linaro.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 13/06/2025 16:04, Dmitry Baryshkov wrote: > On 13/06/2025 17:02, Krzysztof Kozlowski wrote: >> On 13/06/2025 15:55, Dmitry Baryshkov wrote: >>>> >>>> @@ -361,24 +373,47 @@ static int dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll) >>>> >>>> static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll) >>>> { >>>> + unsigned long flags; >>>> u32 data; >>>> >>>> + spin_lock_irqsave(&pll->pll_enable_lock, flags); >>>> + --pll->pll_enable_cnt; >>>> + if (pll->pll_enable_cnt < 0) { >>>> + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); >>>> + DRM_DEV_ERROR_RATELIMITED(&pll->phy->pdev->dev, >>>> + "bug: imbalance in disabling PLL bias\n"); >>>> + return; >>>> + } else if (pll->pll_enable_cnt > 0) { >>>> + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); >>>> + return; >>>> + } /* else: == 0 */ >>>> + >>>> data = readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); >>>> data &= ~DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB; >>>> writel(0, pll->phy->pll_base + REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES); >>>> writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_0); >>>> + spin_unlock_irqrestore(&pll->pll_enable_lock, flags); >>>> ndelay(250); >>> >>> What is this ndelay protecting? Is is to let the hardware to wind down >>> correctly? I'm worried about dsi_pll_disable_pll_bias() beng followed up >>> by dsi_pll_enable_pll_bias() in another thread, which would mean that >>> corresponding writes to the REG_DSI_7nm_PHY_CMN_CTRL_0 can come up >>> without any delay between them. >>> >> >> Great question, but why do you ask me? The code was there already and >> MSM DRM drivers are not something I know and could provide context about. > > Because it's you who are changing the code as you've faced the issue > with recalc_rate. > Heh, the answer is then: I don't know. I think authors of the code could know. Best regards, Krzysztof