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bits=128/128); Mon, 14 Sep 2026 04:47:29 -0700 (PDT) Message-ID: <8acf2491-01f3-49d0-a357-39592ba991dc@oss.qualcomm.com> Date: Mon, 14 Sep 2026 12:47:27 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/6] ASoC: qcom: lpass-va-macro: Add shikra compatible To: Mohammad Rafi Shaik , Srinivas Kandagatla , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai Cc: linux-sound@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260910-add_shikra_support-v2-0-fdd2129c696c@oss.qualcomm.com> <20260910-add_shikra_support-v2-5-fdd2129c696c@oss.qualcomm.com> Content-Language: en-US From: Srinivas Kandagatla In-Reply-To: <20260910-add_shikra_support-v2-5-fdd2129c696c@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 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a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=JLmBH_I5Lc3HKOleWBUA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-ORIG-GUID: _w7OlJ86Upzk4O5F1DhlHmyVj3n0q_JE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-14_03,2026-09-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 priorityscore=1501 suspectscore=0 impostorscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609140167 On 9/10/26 10:46 AM, Mohammad Rafi Shaik wrote: > Add shikra specific VA macro data and register programming needed by > the LPASS codec v4.0 implementation. > > LPASS codec v4.1 extends the VA macro with four adaptive filter (ADPT) > blocks at 0x0800..0x09a4 and requires the FS counter to be bypassed > before it is enabled. > > Add the new registers as a separate reg_default array that is > concatenated with the common defaults at probe time. > > The register layout has to be chosen before the regmap exists, i.e. > before CDC_VA_TOP_CSR_CORE_ID_* can be read, so it comes from match data; > probe then cross checks it against the version reported by the hardware. > > Signed-off-by: Mohammad Rafi Shaik > --- > sound/soc/codecs/lpass-va-macro.c | 228 ++++++++++++++++++++++++++++++++++++-- > 1 file changed, 221 insertions(+), 7 deletions(-) > > diff --git a/sound/soc/codecs/lpass-va-macro.c b/sound/soc/codecs/lpass-va-macro.c > index a3b3af0d7..8353921f7 100644 > --- a/sound/soc/codecs/lpass-va-macro.c > +++ b/sound/soc/codecs/lpass-va-macro.c > @@ -26,6 +26,7 @@ > #define CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004) > #define CDC_VA_FS_CONTROL_EN BIT(0) > #define CDC_VA_FS_COUNTER_CLR BIT(1) > +#define CDC_VA_FS_CNT_BYPASS BIT(7) > #define CDC_VA_CLK_RST_CTRL_SWR_CONTROL (0x0008) > #define CDC_VA_SWR_RESET_MASK BIT(1) > #define CDC_VA_SWR_RESET_ENABLE BIT(1) > @@ -156,7 +157,54 @@ > #define CDC_VA_TX3_TX_PATH_SEC5 (0x05A4) > #define CDC_VA_TX3_TX_PATH_SEC6 (0x05A8) > > +/* LPASS codec v4.1 adaptive filter (ADPT) blocks */ > +#define CDC_VA_CDC_ADPT0_ADPT_CTRL 0x0800 > +#define CDC_VA_ADPT_CTRL_EN_MASK GENMASK(7, 0) > +#define CDC_VA_CDC_ADPT0_ADPT_GAIN_0 0x0804 > +#define CDC_VA_CDC_ADPT0_ADPT_GAIN_1 0x0808 > +#define CDC_VA_CDC_ADPT0_DH_FSM_CTRL 0x080c > +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_0 0x0810 > +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_1 0x0814 > +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_2 0x0818 > +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_3 0x081c > +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_4 0x0820 > +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_5 0x0824 > + > +#define CDC_VA_CDC_ADPT1_ADPT_CTRL 0x0880 > +#define CDC_VA_CDC_ADPT1_ADPT_GAIN_0 0x0884 > +#define CDC_VA_CDC_ADPT1_ADPT_GAIN_1 0x0888 > +#define CDC_VA_CDC_ADPT1_DH_FSM_CTRL 0x088c > +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_0 0x0890 > +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_1 0x0894 > +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_2 0x0898 > +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_3 0x089c > +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_4 0x08a0 > +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_5 0x08a4 > + > +#define CDC_VA_CDC_ADPT2_ADPT_CTRL 0x0900 > +#define CDC_VA_CDC_ADPT2_ADPT_GAIN_0 0x0904 > +#define CDC_VA_CDC_ADPT2_ADPT_GAIN_1 0x0908 > +#define CDC_VA_CDC_ADPT2_DH_FSM_CTRL 0x090c > +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_0 0x0910 > +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_1 0x0914 > +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_2 0x0918 > +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_3 0x091c > +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_4 0x0920 > +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_5 0x0924 > + > +#define CDC_VA_CDC_ADPT3_ADPT_CTRL 0x0980 > +#define CDC_VA_CDC_ADPT3_ADPT_GAIN_0 0x0984 > +#define CDC_VA_CDC_ADPT3_ADPT_GAIN_1 0x0988 > +#define CDC_VA_CDC_ADPT3_DH_FSM_CTRL 0x098c > +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_0 0x0990 > +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_1 0x0994 > +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_2 0x0998 > +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_3 0x099c > +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_4 0x09a0 > +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_5 0x09a4 > + > #define VA_MAX_OFFSET (0x07A8) > +#define VA_4_1_MAX_OFFSET 0x09a4 > > #define VA_MACRO_NUM_DECIMATORS 4 > #define VA_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ > @@ -210,7 +258,6 @@ struct va_macro { > u16 dmic_clk_div; > bool has_swr_master; > bool has_npl_clk; > - > int dec_mode[VA_MACRO_NUM_DECIMATORS]; > struct regmap *regmap; > struct clk *mclk; > @@ -237,6 +284,7 @@ struct va_macro_data { > bool has_swr_master; > bool has_npl_clk; > int version; > + const struct regmap_config *regmap_config; > }; > > static const struct va_macro_data sm8250_va_data = { > @@ -357,6 +405,127 @@ static const struct reg_default va_defaults[] = { > { CDC_VA_TX3_TX_PATH_SEC6, 0x00}, > }; > > +static const struct reg_default va_4_1_defaults[] = { > + /* VA macro */ > + { CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, > + { CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, > + { CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00}, > + { CDC_VA_TOP_CSR_TOP_CFG0, 0x00}, > + { CDC_VA_TOP_CSR_DMIC0_CTL, 0x00}, > + { CDC_VA_TOP_CSR_DMIC1_CTL, 0x00}, > + { CDC_VA_TOP_CSR_DMIC2_CTL, 0x00}, > + { CDC_VA_TOP_CSR_DMIC3_CTL, 0x00}, > + { CDC_VA_TOP_CSR_DMIC_CFG, 0x80}, > + { CDC_VA_TOP_CSR_DEBUG_BUS, 0x00}, > + { CDC_VA_TOP_CSR_DEBUG_EN, 0x00}, > + { CDC_VA_TOP_CSR_TX_I2S_CTL, 0x0C}, > + { CDC_VA_TOP_CSR_I2S_CLK, 0x00}, > + { CDC_VA_TOP_CSR_I2S_RESET, 0x00}, > + { CDC_VA_TOP_CSR_CORE_ID_0, 0x00}, > + { CDC_VA_TOP_CSR_CORE_ID_1, 0x00}, > + { CDC_VA_TOP_CSR_CORE_ID_2, 0x00}, > + { CDC_VA_TOP_CSR_CORE_ID_3, 0x00}, > + { CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE}, > + { CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE}, > + { CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE}, > + { CDC_VA_TOP_CSR_SWR_CTRL, 0x06}, > + /* VA core */ > + { CDC_VA_INP_MUX_ADC_MUX0_CFG0, 0x00}, > + { CDC_VA_INP_MUX_ADC_MUX0_CFG1, 0x00}, > + { CDC_VA_INP_MUX_ADC_MUX1_CFG0, 0x00}, > + { CDC_VA_INP_MUX_ADC_MUX1_CFG1, 0x00}, > + { CDC_VA_INP_MUX_ADC_MUX2_CFG0, 0x00}, > + { CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0x00}, > + { CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0x00}, > + { CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0x00}, > + { CDC_VA_TX0_TX_PATH_CTL, 0x04}, > + { CDC_VA_TX0_TX_PATH_CFG0, 0x10}, > + { CDC_VA_TX0_TX_PATH_CFG1, 0x0B}, > + { CDC_VA_TX0_TX_VOL_CTL, 0x00}, > + { CDC_VA_TX0_TX_PATH_SEC0, 0x00}, > + { CDC_VA_TX0_TX_PATH_SEC1, 0x00}, > + { CDC_VA_TX0_TX_PATH_SEC2, 0x01}, > + { CDC_VA_TX0_TX_PATH_SEC3, 0x3C}, > + { CDC_VA_TX0_TX_PATH_SEC4, 0x20}, > + { CDC_VA_TX0_TX_PATH_SEC5, 0x00}, > + { CDC_VA_TX0_TX_PATH_SEC6, 0x00}, > + { CDC_VA_TX0_TX_PATH_SEC7, 0x25}, > + { CDC_VA_TX1_TX_PATH_CTL, 0x04}, > + { CDC_VA_TX1_TX_PATH_CFG0, 0x10}, > + { CDC_VA_TX1_TX_PATH_CFG1, 0x0B}, > + { CDC_VA_TX1_TX_VOL_CTL, 0x00}, > + { CDC_VA_TX1_TX_PATH_SEC0, 0x00}, > + { CDC_VA_TX1_TX_PATH_SEC1, 0x00}, > + { CDC_VA_TX1_TX_PATH_SEC2, 0x01}, > + { CDC_VA_TX1_TX_PATH_SEC3, 0x3C}, > + { CDC_VA_TX1_TX_PATH_SEC4, 0x20}, > + { CDC_VA_TX1_TX_PATH_SEC5, 0x00}, > + { CDC_VA_TX1_TX_PATH_SEC6, 0x00}, > + { CDC_VA_TX2_TX_PATH_CTL, 0x04}, > + { CDC_VA_TX2_TX_PATH_CFG0, 0x10}, > + { CDC_VA_TX2_TX_PATH_CFG1, 0x0B}, > + { CDC_VA_TX2_TX_VOL_CTL, 0x00}, > + { CDC_VA_TX2_TX_PATH_SEC0, 0x00}, > + { CDC_VA_TX2_TX_PATH_SEC1, 0x00}, > + { CDC_VA_TX2_TX_PATH_SEC2, 0x01}, > + { CDC_VA_TX2_TX_PATH_SEC3, 0x3C}, > + { CDC_VA_TX2_TX_PATH_SEC4, 0x20}, > + { CDC_VA_TX2_TX_PATH_SEC5, 0x00}, > + { CDC_VA_TX2_TX_PATH_SEC6, 0x00}, > + { CDC_VA_TX3_TX_PATH_CTL, 0x04}, > + { CDC_VA_TX3_TX_PATH_CFG0, 0x10}, > + { CDC_VA_TX3_TX_PATH_CFG1, 0x0B}, > + { CDC_VA_TX3_TX_VOL_CTL, 0x00}, > + { CDC_VA_TX3_TX_PATH_SEC0, 0x00}, > + { CDC_VA_TX3_TX_PATH_SEC1, 0x00}, > + { CDC_VA_TX3_TX_PATH_SEC2, 0x01}, > + { CDC_VA_TX3_TX_PATH_SEC3, 0x3C}, > + { CDC_VA_TX3_TX_PATH_SEC4, 0x20}, > + { CDC_VA_TX3_TX_PATH_SEC5, 0x00}, > + { CDC_VA_TX3_TX_PATH_SEC6, 0x00}, > + /* ADPT blocks */ > + { CDC_VA_CDC_ADPT0_ADPT_CTRL, 0x51}, > + { CDC_VA_CDC_ADPT0_ADPT_GAIN_0, 0x11}, > + { CDC_VA_CDC_ADPT0_ADPT_GAIN_1, 0x01}, > + { CDC_VA_CDC_ADPT0_DH_FSM_CTRL, 0x02}, > + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_0, 0x77}, > + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_1, 0x64}, > + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_2, 0x00}, > + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_3, 0x41}, > + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_4, 0x04}, > + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_5, 0x01}, > + { CDC_VA_CDC_ADPT1_ADPT_CTRL, 0x51}, > + { CDC_VA_CDC_ADPT1_ADPT_GAIN_0, 0x11}, > + { CDC_VA_CDC_ADPT1_ADPT_GAIN_1, 0x01}, > + { CDC_VA_CDC_ADPT1_DH_FSM_CTRL, 0x02}, > + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_0, 0x77}, > + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_1, 0x64}, > + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_2, 0x00}, > + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_3, 0x41}, > + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_4, 0x04}, > + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_5, 0x01}, > + { CDC_VA_CDC_ADPT2_ADPT_CTRL, 0x51}, > + { CDC_VA_CDC_ADPT2_ADPT_GAIN_0, 0x11}, > + { CDC_VA_CDC_ADPT2_ADPT_GAIN_1, 0x01}, > + { CDC_VA_CDC_ADPT2_DH_FSM_CTRL, 0x02}, > + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_0, 0x77}, > + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_1, 0x64}, > + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_2, 0x00}, > + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_3, 0x41}, > + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_4, 0x04}, > + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_5, 0x01}, > + { CDC_VA_CDC_ADPT3_ADPT_CTRL, 0x51}, > + { CDC_VA_CDC_ADPT3_ADPT_GAIN_0, 0x11}, > + { CDC_VA_CDC_ADPT3_ADPT_GAIN_1, 0x01}, > + { CDC_VA_CDC_ADPT3_DH_FSM_CTRL, 0x02}, > + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_0, 0x77}, > + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_1, 0x64}, > + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_2, 0x00}, > + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_3, 0x41}, > + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_4, 0x04}, > + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_5, 0x01}, > +}; > + > static bool va_is_rw_register(struct device *dev, unsigned int reg) > { > switch (reg) { > @@ -430,6 +599,10 @@ static bool va_is_rw_register(struct device *dev, unsigned int reg) > case CDC_VA_TX3_TX_PATH_SEC4: > case CDC_VA_TX3_TX_PATH_SEC5: > case CDC_VA_TX3_TX_PATH_SEC6: > + case CDC_VA_CDC_ADPT0_ADPT_CTRL: > + case CDC_VA_CDC_ADPT1_ADPT_CTRL: > + case CDC_VA_CDC_ADPT2_ADPT_CTRL: > + case CDC_VA_CDC_ADPT3_ADPT_CTRL: > return true; > } > > @@ -463,6 +636,27 @@ static const struct regmap_config va_regmap_config = { > .writeable_reg = va_is_rw_register, > }; > > +static const struct regmap_config va_4_1_regmap_config = { > + .name = "va_macro", > + .reg_bits = 32, > + .val_bits = 32, > + .reg_stride = 4, > + .cache_type = REGCACHE_FLAT, Pl use MAPLE here. > + .reg_defaults = va_4_1_defaults, > + .num_reg_defaults = ARRAY_SIZE(va_4_1_defaults), > + .max_register = VA_4_1_MAX_OFFSET, > + .volatile_reg = va_is_volatile_register, > + .readable_reg = va_is_readable_register, > + .writeable_reg = va_is_rw_register, > +}; > + > +static const struct va_macro_data shikra_va_data = { > + .has_swr_master = true, > + .has_npl_clk = true, > + .version = LPASS_CODEC_VERSION_4_1, > + .regmap_config = &va_4_1_regmap_config, > +}; > + > static int va_clk_rsc_fs_gen_request(struct va_macro *va, bool enable) > { > struct regmap *regmap = va->regmap; > @@ -471,10 +665,14 @@ static int va_clk_rsc_fs_gen_request(struct va_macro *va, bool enable) > regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, > CDC_VA_MCLK_CONTROL_EN, > CDC_VA_MCLK_CONTROL_EN); > - /* clear the fs counter */ > + > regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, > CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR, > CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR); > + > + if (lpass_macro_get_codec_version() >= LPASS_CODEC_VERSION_4_1) same comment as in 4/5 patch use a flag. > + regmap_set_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, > + CDC_VA_FS_CNT_BYPASS); > regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, > CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR, > CDC_VA_FS_CONTROL_EN); > @@ -503,7 +701,7 @@ static int va_macro_mclk_enable(struct va_macro *va, bool mclk_enable) > if (mclk_enable) { > va_clk_rsc_fs_gen_request(va, true); > regcache_mark_dirty(regmap); > - regcache_sync_region(regmap, 0x0, VA_MAX_OFFSET); > + regcache_sync_region(regmap, 0x0, regmap_get_max_register(regmap)); > } else { > va_clk_rsc_fs_gen_request(va, false); > } > @@ -749,6 +947,7 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, > unsigned int decimator; > u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg; > u16 tx_gain_ctl_reg; > + u16 adpt_ctrl_reg; > u8 hpf_cut_off_freq; > > struct va_macro *va = snd_soc_component_get_drvdata(comp); > @@ -763,6 +962,7 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, > VA_MACRO_TX_PATH_OFFSET * decimator; > tx_gain_ctl_reg = CDC_VA_TX0_TX_VOL_CTL + > VA_MACRO_TX_PATH_OFFSET * decimator; > + adpt_ctrl_reg = CDC_VA_CDC_ADPT0_ADPT_CTRL + decimator * VA_MACRO_TX_PATH_OFFSET; > > switch (event) { > case SND_SOC_DAPM_PRE_PMU: > @@ -772,6 +972,10 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, > /* Enable TX PGA Mute */ > break; > case SND_SOC_DAPM_POST_PMU: > + if (lpass_macro_get_codec_version() >= LPASS_CODEC_VERSION_4_1) either move to switch or something but not >= > + snd_soc_component_update_bits(comp, adpt_ctrl_reg, > + CDC_VA_ADPT_CTRL_EN_MASK, 0x00); > + > /* Enable TX CLK */ > snd_soc_component_update_bits(comp, tx_vol_ctl_reg, > CDC_VA_TX_PATH_CLK_EN_MASK, > @@ -1526,6 +1730,14 @@ static int va_macro_set_lpass_codec_version(struct va_macro *va) > default: > break; > } > + } else if (maj == 4) { > + switch (min) { > + case 1: > + version = LPASS_CODEC_VERSION_4_1; > + break; > + default: > + break; > + } > } > > if (version == LPASS_CODEC_VERSION_UNKNOWN) { > @@ -1556,6 +1768,7 @@ static int va_macro_probe(struct platform_device *pdev) > return -ENOMEM; > > va->dev = dev; > + data = of_device_get_match_data(dev); > > va->macro = devm_clk_get_optional(dev, "macro"); > if (IS_ERR(va->macro)) > @@ -1592,15 +1805,15 @@ static int va_macro_probe(struct platform_device *pdev) > goto err; > } > > - va->regmap = devm_regmap_init_mmio(dev, base, &va_regmap_config); > + dev_set_drvdata(dev, va); > + > + va->regmap = devm_regmap_init_mmio(dev, base, > + data->regmap_config ?: &va_regmap_config); > if (IS_ERR(va->regmap)) { > ret = -EINVAL; > goto err; > } > > - dev_set_drvdata(dev, va); > - > - data = of_device_get_match_data(dev); > va->has_swr_master = data->has_swr_master; > va->has_npl_clk = data->has_npl_clk; > > @@ -1775,6 +1988,7 @@ static const struct of_device_id va_macro_dt_match[] = { > { .compatible = "qcom,sm8450-lpass-va-macro", .data = &sm8450_va_data }, > { .compatible = "qcom,sm8550-lpass-va-macro", .data = &sm8550_va_data }, > { .compatible = "qcom,sc8280xp-lpass-va-macro", .data = &sm8450_va_data }, > + { .compatible = "qcom,shikra-lpass-va-macro", .data = &shikra_va_data }, > {} > }; > MODULE_DEVICE_TABLE(of, va_macro_dt_match); >