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From: Kai Huang <kai.huang@intel.com>
To: "Tian, Kevin" <kevin.tian@intel.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
	"Gleixner, Thomas" <thomas.gleixner@intel.com>
Cc: "Hansen, Dave" <dave.hansen@intel.com>, "Christopherson,,
	Sean" <seanjc@google.com>,
	"pbonzini@redhat.com" <pbonzini@redhat.com>,
	"kirill.shutemov@linux.intel.com"
	<kirill.shutemov@linux.intel.com>,
	"sathyanarayanan.kuppuswamy@linux.intel.com" 
	<sathyanarayanan.kuppuswamy@linux.intel.com>,
	"peterz@infradead.org" <peterz@infradead.org>,
	"Luck, Tony" <tony.luck@intel.com>,
	"ak@linux.intel.com" <ak@linux.intel.com>,
	"Williams, Dan J" <dan.j.williams@intel.com>,
	"Yamahata, Isaku" <isaku.yamahata@intel.com>
Subject: Re: [PATCH v2 04/21] x86/virt/tdx: Add skeleton for detecting and initializing TDX on demand
Date: Tue, 29 Mar 2022 16:17:18 +1300	[thread overview]
Message-ID: <8ad4e66a71e6a4e7af1ce08c9776fe2097cfeff6.camel@intel.com> (raw)
In-Reply-To: <15c0212fc4ff591a878369ea6ae964e43574a8d9.camel@intel.com>

On Tue, 2022-03-29 at 16:10 +1300, Kai Huang wrote:
> > > > 
> > > > *all cpus* is questionable.
> > > > 
> > > > Say BIOS enabled 8 CPUs: [0 - 7]
> > > > 
> > > > cpu_present_map covers [0 - 5], due to nr_cpus=6
> > > > 
> > > > You compared cpus_booted_once_mask to cpu_present_mask so if
> > > maxcpus
> > > > is set to a number < nr_cpus SEAMRR is considered disabled because you
> > > > cannot verify CPUs between [max_cpus, nr_cpus).
> 
> Sorry my bad.  We can verify CPUs between [max_cpus, nr_cpus).  When any cpu
> within that range becomes online, the detection code is run.  The paranoid
> check
> in seamrr_enabled() is used to check whether all cpus within [max_cpus,
> nr_cpus)
> (if there's any -- cpus within [0, max_cpus) are up during boot) have been
> brought up at least once. 
> 
> > > 
> > > SEAMRR is not considered as disabled in this case, at least in my
> > > intention.
> > 
> > the function is called seamrr_enabled(), and false is returned if above
> > check is not passed. So it is the intention from the code.
> 
> The false is returned if something error is discovered among cpus [0 -
> present_cpus].  It returns true even if we cannot verify [present_cpus,
> bios_enabled_cpus).

Sorry typo.  Not "something error is discovered among cpus [0 - present_cpus)",
but "when there's any cpu within [0 - present_cpus) hasn't been brought up
once".
 
> 
> > 
> > > My
> > > understanding on the spec is if SEAMRR is configured as enabled on one
> > > core
> > > (the
> > > SEAMRR MSRs are core-scope), the SEAMCALL instruction can work on that
> > > core.  It
> > > is TDX's requirement that some SEAMCALL needs to be done on all BIOS-
> > > enabled
> > > CPUs to finish TDX initialization, but not SEAM's.
> > > 
> > > From this perspective, if we forget TDX at this moment but talk about SEAM
> > > alone, it might make sense to not just treat SEAMRR as disabled if kernel
> > > usable
> > > cpus are limited by 'nr_cpus'.  The chance that BIOS misconfigured SEAMRR
> > > is
> > > really rare.  If kernel can detect potential BIOS misconfiguration, it
> > > should do
> > > it.  Otherwise, perhaps it's more reasonable not to just treat SEAM as
> > > disabled.
> > 
> > My problem is just that you didn't adopt consistency policy for CPUs in
> > [maxcpus, nr_cpus) and CPUs in [nr_cpus, nr_bios_enabled_cpus). This is
> > the only trouble to me no matter what policy you want to pursue...
> 
> Let's separate SEAMRR detection and TDX initialization.  The paranoid check is
> only for SEAM detection, but not for TDX initialization.  As I said, it is
> TDX's
> requirement that some SEAMCALL must be run on all bios-enabled cpus, but not
> SEAM's.
> 
> 


  reply	other threads:[~2022-03-29  3:17 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-13 10:49 [PATCH v2 00/21] TDX host kernel support Kai Huang
2022-03-13 10:49 ` [PATCH v2 01/21] x86/virt/tdx: Detect SEAM Kai Huang
2022-03-23  3:21   ` Tian, Kevin
2022-03-28  3:55     ` Kai Huang
2022-03-28  8:10       ` Tian, Kevin
2022-03-29 17:52         ` Isaku Yamahata
2022-03-29 23:28           ` Kai Huang
2022-03-13 10:49 ` [PATCH v2 02/21] x86/virt/tdx: Detect TDX private KeyIDs Kai Huang
2022-03-13 10:49 ` [PATCH v2 03/21] x86/virt/tdx: Implement the SEAMCALL base function Kai Huang
2022-03-23  3:35   ` Tian, Kevin
2022-03-28  1:41     ` Kai Huang
2022-03-28  8:16       ` Tian, Kevin
2022-03-28  9:10         ` Kai Huang
2022-03-13 10:49 ` [PATCH v2 04/21] x86/virt/tdx: Add skeleton for detecting and initializing TDX on demand Kai Huang
2022-03-23  6:49   ` Tian, Kevin
2022-03-28  1:57     ` Kai Huang
2022-03-28  8:26       ` Tian, Kevin
2022-03-28  9:24         ` Kai Huang
2022-03-28 11:47           ` Tian, Kevin
2022-03-28 22:55             ` Kai Huang
2022-03-29  2:36               ` Tian, Kevin
2022-03-29  3:10                 ` Kai Huang
2022-03-29  3:17                   ` Kai Huang [this message]
2022-03-13 10:49 ` [PATCH v2 05/21] x86/virt/tdx: Detect P-SEAMLDR and TDX module Kai Huang
2022-03-13 10:49 ` [PATCH v2 06/21] x86/virt/tdx: Shut down TDX module in case of error Kai Huang
2022-03-13 10:49 ` [PATCH v2 07/21] x86/virt/tdx: Do TDX module global initialization Kai Huang
2022-03-13 10:49 ` [PATCH v2 08/21] x86/virt/tdx: Do logical-cpu scope TDX module initialization Kai Huang
2022-03-13 10:49 ` [PATCH v2 09/21] x86/virt/tdx: Get information about TDX module and convertible memory Kai Huang
2022-03-24 17:43   ` Isaku Yamahata
2022-03-28  1:30     ` Kai Huang
2022-03-28 20:22       ` Isaku Yamahata
2022-03-28 20:30         ` Dave Hansen
2022-03-28 23:40           ` Kai Huang
2022-03-28 23:44             ` Dave Hansen
2022-03-29  0:04               ` Kai Huang
2022-03-13 10:49 ` [PATCH v2 10/21] x86/virt/tdx: Add placeholder to coveret all system RAM as TDX memory Kai Huang
2022-03-13 10:49 ` [PATCH v2 11/21] x86/virt/tdx: Choose to use " Kai Huang
2022-03-13 10:49 ` [PATCH v2 12/21] x86/virt/tdx: Create TDMRs to cover all system RAM Kai Huang
2022-03-13 10:49 ` [PATCH v2 13/21] x86/virt/tdx: Allocate and set up PAMTs for TDMRs Kai Huang
2022-03-24 18:06   ` Isaku Yamahata
2022-03-28  1:16     ` Kai Huang
2022-03-13 10:49 ` [PATCH v2 14/21] x86/virt/tdx: Set up reserved areas for all TDMRs Kai Huang
2022-03-13 10:49 ` [PATCH v2 15/21] x86/virt/tdx: Reserve TDX module global KeyID Kai Huang
2022-03-13 10:49 ` [PATCH v2 16/21] x86/virt/tdx: Configure TDX module with TDMRs and " Kai Huang
2022-03-13 10:49 ` [PATCH v2 17/21] x86/virt/tdx: Configure global KeyID on all packages Kai Huang
2022-03-24 18:18   ` isaku.yamahata
2022-03-28  1:19     ` Kai Huang
2022-03-13 10:49 ` [PATCH v2 18/21] x86/virt/tdx: Initialize all TDMRs Kai Huang
2022-03-13 10:49 ` [PATCH v2 19/21] x86: Flush cache of TDX private memory during kexec() Kai Huang
2022-03-13 10:50 ` [PATCH v2 20/21] x86/virt/tdx: Add kernel command line to opt-in TDX host support Kai Huang
2022-03-13 10:50 ` [PATCH v2 21/21] Documentation/x86: Add documentation for " Kai Huang

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