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[94.29.32.67]) by smtp.googlemail.com with ESMTPSA id c10sm1821085lfp.65.2019.09.22.15.35.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 22 Sep 2019 15:35:03 -0700 (PDT) Subject: Re: [PATCH v4 1/2] soc/tegra: pmc: Query PCLK clock rate at probe time From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org References: <20190804202927.15014-1-digetx@gmail.com> Message-ID: <8ad9dea9-efb5-4be3-0a14-651df468d80d@gmail.com> Date: Mon, 23 Sep 2019 01:35:02 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20190804202927.15014-1-digetx@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 04.08.2019 23:29, Dmitry Osipenko пишет: > It is possible to get a lockup if kernel decides to enter LP2 cpuidle > from some clk-notifier, in that case CCF's "prepare" mutex is kept locked > and thus clk_get_rate(pclk) blocks on the same mutex with interrupts being > disabled. > > Signed-off-by: Dmitry Osipenko > --- > > Changelog: > > v4: Added clk-notifier to track PCLK rate-changes, which may become useful > in the future. That's done in response to v3 review comment from Peter > De Schrijver. > > Now properly handling case where clk pointer is intentionally NULL on > the driver's probe. > > v3: Changed commit's message because I actually recalled what was the > initial reason for the patch, since the problem reoccurred once again. > > v2: Addressed review comments that were made by Jon Hunter to v1 by > not moving the memory barrier, replacing one missed clk_get_rate() > with pmc->rate, handling possible clk_get_rate() error on probe and > slightly adjusting the commits message. > > drivers/soc/tegra/pmc.c | 71 ++++++++++++++++++++++++++++++----------- > 1 file changed, 53 insertions(+), 18 deletions(-) > > diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c > index 9f9c1c677cf4..4e44943d0b26 100644 > --- a/drivers/soc/tegra/pmc.c > +++ b/drivers/soc/tegra/pmc.c > @@ -309,6 +309,7 @@ static const char * const tegra210_reset_sources[] = { > * @pctl_dev: pin controller exposed by the PMC > * @domain: IRQ domain provided by the PMC > * @irq: chip implementation for the IRQ domain > + * @clk_nb: pclk clock changes handler > */ > struct tegra_pmc { > struct device *dev; > @@ -344,6 +345,8 @@ struct tegra_pmc { > > struct irq_domain *domain; > struct irq_chip irq; > + > + struct notifier_block clk_nb; > }; > > static struct tegra_pmc *pmc = &(struct tegra_pmc) { > @@ -1192,7 +1195,7 @@ static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id, > return err; > > if (pmc->clk) { > - rate = clk_get_rate(pmc->clk); > + rate = pmc->rate; > if (!rate) { > dev_err(pmc->dev, "failed to get clock rate\n"); > return -ENODEV; > @@ -1433,6 +1436,7 @@ void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) > void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) > { > unsigned long long rate = 0; > + u64 ticks; > u32 value; > > switch (mode) { > @@ -1441,31 +1445,22 @@ void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) > break; > > case TEGRA_SUSPEND_LP2: > - rate = clk_get_rate(pmc->clk); > + rate = pmc->rate; > break; > > default: > break; > } > > - if (WARN_ON_ONCE(rate == 0)) > - rate = 100000000; > - > - if (rate != pmc->rate) { > - u64 ticks; > - > - ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; > - do_div(ticks, USEC_PER_SEC); > - tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); > + ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; > + do_div(ticks, USEC_PER_SEC); > + tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); > > - ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; > - do_div(ticks, USEC_PER_SEC); > - tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); > + ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; > + do_div(ticks, USEC_PER_SEC); > + tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); > > - wmb(); > - > - pmc->rate = rate; > - } > + wmb(); > > value = tegra_pmc_readl(pmc, PMC_CNTRL); > value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; > @@ -2019,6 +2014,20 @@ static int tegra_pmc_irq_init(struct tegra_pmc *pmc) > return 0; > } > > +static int tegra_pmc_clk_notify_cb(struct notifier_block *nb, > + unsigned long action, void *ptr) > +{ > + struct clk_notifier_data *data = ptr; > + struct tegra_pmc *pmc; > + > + if (action == POST_RATE_CHANGE) { > + pmc = container_of(nb, struct tegra_pmc, clk_nb); > + pmc->rate = data->new_rate; > + } > + > + return NOTIFY_OK; > +} > + > static int tegra_pmc_probe(struct platform_device *pdev) > { > void __iomem *base; > @@ -2082,6 +2091,30 @@ static int tegra_pmc_probe(struct platform_device *pdev) > pmc->clk = NULL; > } > > + /* > + * PCLK clock rate can't be retrieved using CLK API because it > + * causes lockup if CPU enters LP2 idle state from some other > + * CLK notifier, hence we're caching the rate's value locally. > + */ > + if (pmc->clk) { > + pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; > + err = clk_notifier_register(pmc->clk, &pmc->clk_nb); > + if (err) { > + dev_err(&pdev->dev, > + "failed to register clk notifier\n"); > + return err; > + } > + > + pmc->rate = clk_get_rate(pmc->clk); > + } > + > + if (!pmc->rate) { > + if (pmc->clk) > + dev_err(&pdev->dev, "failed to get pclk rate\n"); > + > + pmc->rate = 100000000; > + } > + > pmc->dev = &pdev->dev; > > tegra_pmc_init(pmc); > @@ -2133,6 +2166,8 @@ static int tegra_pmc_probe(struct platform_device *pdev) > cleanup_sysfs: > device_remove_file(&pdev->dev, &dev_attr_reset_reason); > device_remove_file(&pdev->dev, &dev_attr_reset_level); > + clk_notifier_unregister(pmc->clk, &pmc->clk_nb); > + > return err; > } > > Hello Peter and Jon, You had some comments that have been addressed, does this version look good to you? ACK?