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[75.142.250.213]) by smtp.gmail.com with ESMTPSA id v18sm2833857qkv.62.2021.01.26.06.58.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 26 Jan 2021 06:58:41 -0800 (PST) Subject: Re: [PATCH v2 2/4] mfd: intel-m10-bmc: Simplify the legacy version reg definition To: Xu Yilun , lee.jones@linaro.org, linux-kernel@vger.kernel.org Cc: matthew.gerlach@linux.intel.com, russell.h.weight@intel.com, lgoncalv@redhat.com, hao.wu@intel.com References: <1611643836-7183-1-git-send-email-yilun.xu@intel.com> <1611643836-7183-3-git-send-email-yilun.xu@intel.com> From: Tom Rix Message-ID: <8b101def-1969-97ab-0c56-732e9159b4e7@redhat.com> Date: Tue, 26 Jan 2021 06:58:39 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0 MIME-Version: 1.0 In-Reply-To: <1611643836-7183-3-git-send-email-yilun.xu@intel.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Content-Language: en-US Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 1/25/21 10:50 PM, Xu Yilun wrote: > The version register is the only one in the legacy I/O space to be > accessed, so it is not necessary to define the legacy base & version > register offset. A direct definition of the legacy version register > address would be fine. > > Signed-off-by: Xu Yilun > --- > drivers/mfd/intel-m10-bmc.c | 12 +++++------- > include/linux/mfd/intel-m10-bmc.h | 2 +- > 2 files changed, 6 insertions(+), 8 deletions(-) Thanks for adding M10BMC_LEGACY_BUILD_VER Reviewed-by: Tom Rix > diff --git a/drivers/mfd/intel-m10-bmc.c b/drivers/mfd/intel-m10-bmc.c > index b84579b..aad86f0 100644 > --- a/drivers/mfd/intel-m10-bmc.c > +++ b/drivers/mfd/intel-m10-bmc.c > @@ -74,16 +74,14 @@ static int check_m10bmc_version(struct intel_m10bmc *ddata) > > /* > * This check is to filter out the very old legacy BMC versions, > - * M10BMC_LEGACY_SYS_BASE is the offset to this old block of mmio > - * registers. In the old BMC chips, the BMC version info is stored > - * in this old version register (M10BMC_LEGACY_SYS_BASE + > - * M10BMC_BUILD_VER), so its read out value would have not been > - * LEGACY_INVALID (0xffffffff). But in new BMC chips that the > + * 0x300400 is the offset to this old block of mmio registers. In the > + * old BMC chips, the BMC version info is stored in this old version > + * register (0x300400 + 0x68), so its read out value would have not > + * been LEGACY_INVALID (0xffffffff). But in new BMC chips that the > * driver supports, the value of this register should be > * LEGACY_INVALID. > */ > - ret = m10bmc_raw_read(ddata, > - M10BMC_LEGACY_SYS_BASE + M10BMC_BUILD_VER, &v); > + ret = m10bmc_raw_read(ddata, M10BMC_LEGACY_BUILD_VER, &v); > if (ret) > return -ENODEV; > > diff --git a/include/linux/mfd/intel-m10-bmc.h b/include/linux/mfd/intel-m10-bmc.h > index 06da62c..99f44b1 100644 > --- a/include/linux/mfd/intel-m10-bmc.h > +++ b/include/linux/mfd/intel-m10-bmc.h > @@ -9,7 +9,7 @@ > > #include > > -#define M10BMC_LEGACY_SYS_BASE 0x300400 > +#define M10BMC_LEGACY_BUILD_VER 0x300468 > #define M10BMC_SYS_BASE 0x300800 > #define M10BMC_MEM_END 0x1fffffff >