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Wed, 03 Jul 2024 17:47:11 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 463HlAFU021100 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 3 Jul 2024 17:47:10 GMT Received: from [10.216.27.55] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 3 Jul 2024 10:47:04 -0700 Message-ID: <8b19c43e-6b13-4b09-9498-ee0b24749d3f@quicinc.com> Date: Wed, 3 Jul 2024 23:17:01 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 6/8] clk: qcom: Add support for Display clock Controllers on SA8775P From: Taniya Das To: Konrad Dybcio , Bjorn Andersson , Michael Turquette , "Stephen Boyd" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski CC: , , , , , References: <20240612-sa8775p-mm-clock-controllers-v1-0-db295a846ee7@quicinc.com> <20240612-sa8775p-mm-clock-controllers-v1-6-db295a846ee7@quicinc.com> <37bbd466-742a-4a23-b3f7-97f8da109608@linaro.org> <053e047b-7594-48bc-ac1b-2368c0c8f1cc@quicinc.com> Content-Language: en-US In-Reply-To: <053e047b-7594-48bc-ac1b-2368c0c8f1cc@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 8H2dPhFn5YhAlR8i7vPvW68GStYIusos X-Proofpoint-ORIG-GUID: 8H2dPhFn5YhAlR8i7vPvW68GStYIusos X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-03_12,2024-07-03_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 mlxlogscore=955 priorityscore=1501 adultscore=0 mlxscore=0 impostorscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407030132 On 6/21/2024 10:03 AM, Taniya Das wrote: >> Please merge this into one to save on boilerplate, take a look >> at dispcc-sc8280xp.c >> > > I did take a look at the dispcc for SC8280XP before posting the series, > but it kind of looked tricky to add fixes for a particular dispcc. > Debugging could also be difficult in my opinion. > Though I understand that we are trying to optimize by re-using few > common structures/probe but from clocks side they are all redefined. > That was the reason to keep them separate. Konrad, are you good with the proposal to keep the two instance of display clock controllers as separate drivers? As I looking to post the next patch series, please let me know your comments. -- Thanks & Regards, Taniya Das.