From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5D1BC433EF for ; Thu, 17 Mar 2022 12:07:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233424AbiCQMIZ (ORCPT ); Thu, 17 Mar 2022 08:08:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233416AbiCQMIX (ORCPT ); Thu, 17 Mar 2022 08:08:23 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DCA81D59C1 for ; Thu, 17 Mar 2022 05:07:06 -0700 (PDT) X-UUID: 0ac663a97f25400ba5128c5806cf542d-20220317 X-UUID: 0ac663a97f25400ba5128c5806cf542d-20220317 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 962720090; Thu, 17 Mar 2022 20:06:50 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 17 Mar 2022 20:06:48 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 17 Mar 2022 20:06:44 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 17 Mar 2022 20:06:44 +0800 Message-ID: <8b331befede093265cd9fc0773000c1bf715a2c8.camel@mediatek.com> Subject: Re: [PATCH v3,3/4] drm/mediatek: keep dsi as LP00 before dcs cmds transfer From: Rex-BC Chen To: , , , , , CC: , , , , , Date: Thu, 17 Mar 2022 20:06:44 +0800 In-Reply-To: <1647503611-13144-4-git-send-email-xinlei.lee@mediatek.com> References: <1647503611-13144-1-git-send-email-xinlei.lee@mediatek.com> <1647503611-13144-4-git-send-email-xinlei.lee@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello Xinlei, On Thu, 2022-03-17 at 15:53 +0800, xinlei.lee@mediatek.com wrote: > From: Jitao Shi > > To comply with the panel sequence, hold the mipi signal to LP00 Could you provide a example panel power sequence to let me understand that? Maybe you can put them in commit message. > before the dcs cmds transmission, > and pull the mipi signal high from LP00 to LP11 until the start of > the dcs cmds transmission. Maybe you can try to write as: To comply with... - Hold the mipi signal... - Pul the miip signal high.... > If dsi is not in cmd mode, then dsi will pull the mipi signal high in > the mtk_output_dsi_enable function. > > Fixes: 2dd8075d2185 ("drm/mediatek: mtk_dsi: Use the drm_panel_bridge > API") > Can you remove this blank line? > Signed-off-by: Jitao Shi > Signed-off-by: Xinlei Lee > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 31 +++++++++++++++++++++++----- > -- > 1 file changed, 24 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c > b/drivers/gpu/drm/mediatek/mtk_dsi.c > index e33caaca11a7..b509d59235e2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -203,6 +203,7 @@ struct mtk_dsi { > struct mtk_phy_timing phy_timing; > int refcount; > bool enabled; > + bool lanes_ready; > u32 irq_data; > wait_queue_head_t irq_wait_queue; > const struct mtk_dsi_driver_data *driver_data; > @@ -654,13 +655,6 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) > mtk_dsi_config_vdo_timing(dsi); > mtk_dsi_set_interrupt_enable(dsi); > > - mtk_dsi_rxtx_control(dsi); > - usleep_range(30, 100); > - mtk_dsi_reset_dphy(dsi); > - mtk_dsi_clk_ulp_mode_leave(dsi); > - mtk_dsi_lane0_ulp_mode_leave(dsi); > - mtk_dsi_clk_hs_mode(dsi, 0); > - > return 0; > err_disable_engine_clk: > clk_disable_unprepare(dsi->engine_clk); > @@ -689,6 +683,8 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi) > clk_disable_unprepare(dsi->digital_clk); > > phy_power_off(dsi->phy); > + > + dsi->lanes_ready = false; > } > > static void mtk_output_dsi_enable(struct mtk_dsi *dsi) > @@ -696,6 +692,16 @@ static void mtk_output_dsi_enable(struct mtk_dsi > *dsi) > if (dsi->enabled) > return; > > + if (!dsi->lanes_ready) { > + dsi->lanes_ready = true; > + mtk_dsi_rxtx_control(dsi); > + usleep_range(30, 100); > + mtk_dsi_reset_dphy(dsi); > + mtk_dsi_clk_ulp_mode_leave(dsi); > + mtk_dsi_lane0_ulp_mode_leave(dsi); > + mtk_dsi_clk_hs_mode(dsi, 0); > + } > + > mtk_dsi_set_mode(dsi); > mtk_dsi_clk_hs_mode(dsi, 1); > > @@ -995,6 +1001,17 @@ static ssize_t mtk_dsi_host_transfer(struct > mipi_dsi_host *host, > if (MTK_DSI_HOST_IS_READ(msg->type)) > irq_flag |= LPRX_RD_RDY_INT_FLAG; > > + if (!dsi->lanes_ready) { > + dsi->lanes_ready = true; > + mtk_dsi_rxtx_control(dsi); > + usleep_range(30, 100); > + mtk_dsi_reset_dphy(dsi); > + mtk_dsi_clk_ulp_mode_leave(dsi); > + mtk_dsi_lane0_ulp_mode_leave(dsi); > + mtk_dsi_clk_hs_mode(dsi, 0); The drivers are the same with previous modification. I think you can use a funtion for them? > + msleep(20); Why delay 20ms but not in mtk_output_dsi_enable? BRs, Rex > + } > + > ret = mtk_dsi_host_send_cmd(dsi, msg, irq_flag); > if (ret) > goto restore_dsi_mode;