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Wed, 21 Oct 2026 04:50:06 -0700 (PDT) Received: from [10.217.240.81] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-367405ed2absm8043559eec.5.2026.10.21.04.50.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Oct 2026 04:50:06 -0700 (PDT) Message-ID: <8b470cbe-d06b-46ea-b928-bbf7dc1c158b@oss.qualcomm.com> Date: Wed, 21 Oct 2026 17:19:59 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] soc: qcom: llcc: add LCP/SRP DDR DRAM ECC register offsets To: Jonathan Cameron Cc: Bjorn Andersson , Konrad Dybcio , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Manivannan Sadhasivam , Borislav Petkov , Tony Luck , Conor Dooley , Abel Vesa , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org References: <20261014-master-v1-0-aba3cfcfbac9@oss.qualcomm.com> <20261014-master-v1-2-aba3cfcfbac9@oss.qualcomm.com> <20261016182014.7d2d8bbe@jic23-hlaptop> Content-Language: en-US From: Faiyaz Mohammed In-Reply-To: <20261016182014.7d2d8bbe@jic23-hlaptop> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=YuKa1IYX c=1 sm=1 tr=0 ts=6ad8a6f0 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=yu8sOhoR8PlAKUki7sMA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDA0NyBTYWx0ZWRfXy4ULyx/IASdu fqYjq1rWIRQX/5MIRdqHYIWmfG9H55pPP6mnM/1Tv8QeRvtK9sySmMHh4D69eL6+f5SpDAftrfy uAiZys1ZtPdvwZ9H8IpYqK/mtrjnAy8= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDA0NyBTYWx0ZWRfX4PL7mhiYzvOG DsLjSyIyApD9/Wca+Q33hzDhm0r9wwKORY3BH7Fke4eH7yQrqSOH47pYctfArNmjVETEtV6rLog ARSmoH8abgGTCXd2ccRRF9aw2o6MRU27VMxuIB0FaEVqMF3LEssrMpm6F89U3wN0qScUQjZRaMZ CWHRNLC6G3fl6Wchsfer4z6pvN5spjbXg26qnPgPaa2WUq9UDLc9CeJeQkLpBXe6Qin6zC9V7Y/ qxUM28CiG9O82TQ4rAvufKcuLOYTlerOyBXro+V+ESngk5lJejU3AVjnixeewcsqt25ja47ShkB mI5nMRbGn0aNdNL9Szvru61oz9Pzz1Db+O7R5slnnJFtdX2/ol/29f3xiUOV2Ql25f5sLb4OjXW /yYWrpULmexQEB5X+4PecV2SW0i2JCAfSOiY/wvW0qzAKthmMxMuIrzwOS141HrGITOtmhsyH8d N/IQ+iMtLrq7VHkVz5Q== X-Proofpoint-GUID: DXQM_ARsI5H5rBdQhE9qdiifq8KronI2 X-Proofpoint-ORIG-GUID: DXQM_ARsI5H5rBdQhE9qdiifq8KronI2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-21_03,2026-10-21_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 suspectscore=0 spamscore=0 clxscore=1015 phishscore=0 adultscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210047 On 16-10-2026 22:50, Jonathan Cameron wrote: > On Wed, 14 Oct 2026 21:26:17 +0530 > Faiyaz Mohammed wrote: > >> Add LCP/SRP ECC register offsets to struct llcc_edac_reg_offset and >> create llcc_lcp_srp_edac_reg_offset for QCM2390, leaving the shared >> llcc_v2_1_edac_reg_offset table unchanged. Switch shikra_cfg to the >> new table so other platforms with the same block can reuse it. >> >> Add lcp_irq to struct llcc_drv_data and retrieve the optional second >> interrupt in qcom_llcc_probe(), propagating non-absence errors so the >> driver defers correctly. >> >> Signed-off-by: Faiyaz Mohammed > Hi Faiyaz, > > One comment on existing code + a suggestion to tidy the new stuff > up a little. > > That global for drv_data is less than ideal, but given you are touching > the driver please tidy up initial assignment to use INIT_ERR_PTR() > > Hi Jonathan, Done. >> static const struct llcc_edac_reg_offset llcc_v6_edac_reg_offset = { >> .trp_ecc_error_status0 = 0x47448, >> .trp_ecc_error_status1 = 0x47450, >> @@ -4767,7 +4802,7 @@ static const struct qcom_llcc_config shikra_cfg[] = { >> .sct_data = shikra_data, >> .size = ARRAY_SIZE(shikra_data), >> .reg_offset = llcc_v2_1_reg_offset, >> - .edac_reg_offset = &llcc_v2_1_edac_reg_offset, >> + .edac_reg_offset = &llcc_lcp_srp_edac_reg_offset, >> .irq_configured = true, >> }, >> }; >> @@ -5798,7 +5833,13 @@ static int qcom_llcc_probe(struct platform_device *pdev) >> if (drv_data->ecc_irq < 0 && drv_data->ecc_irq != -ENXIO) >> return dev_err_probe(&pdev->dev, drv_data->ecc_irq, >> "failed to get IRQ resource\n"); > > Unrelated to your patch, but why don't we need that tiny bit of error cleanup under > goto err for this path? That use of a global is not the best anyway, but none > the less I'd expect either some consistency or a comment on why not in the above > path. > Good point — changed lcp_irq to use return dev_err_probe() to be consistent with the adjacent ecc_irq path. >> - >> + if (cfg->edac_reg_offset && cfg->edac_reg_offset->lcp_srp_interrupt_enable) { >> + drv_data->lcp_irq = platform_get_irq_optional(pdev, 1); >> + if (drv_data->lcp_irq < 0 && drv_data->lcp_irq != -ENXIO) { >> + ret = drv_data->lcp_irq; >> + goto err; >> + } > > Maybe it's local style, but generally I'd put the value in ret until you've checked validty > then copy it to the good location. > > ret = platform_get_irq_optional(pdev, 1); > if (ret < 0 && ret != -ENXIO) > goto err; > drv_data->lcp_irq = ret; > Both more compact and obvious when we trust the value to be good. > > Agreed, restructured accordingly. Will repost as v2. >> + } >> drv_data->edac_reg_offset = cfg->edac_reg_offset; >> drv_data->ecc_irq_configured = cfg->irq_configured; >> drv_data->dev = dev; > Thanks & regards, Mohammed Faiyaz