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X-CSE-ConnectionGUID: yCHPPR1MSO6+/ZEE3ZLl1A== X-CSE-MsgGUID: PxE8pE5PS0ez0tXdzqIH6A== X-IronPort-AV: E=McAfee;i="6800,10657,11663"; a="80544498" X-IronPort-AV: E=Sophos;i="6.21,206,1763452800"; d="scan'208";a="80544498" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jan 2026 10:27:27 -0800 X-CSE-ConnectionGUID: 010MR2iNRXylDp0CsyqRwQ== X-CSE-MsgGUID: yr8Mo8EWRxi/NWjvcuUb4g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,206,1763452800"; d="scan'208";a="202782885" Received: from dnelso2-mobl.amr.corp.intel.com (HELO [10.125.109.101]) ([10.125.109.101]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jan 2026 10:27:27 -0800 Message-ID: <8b627a53-a7c4-4d8e-887d-1594f699e035@intel.com> Date: Tue, 6 Jan 2026 11:27:25 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] PCI/portdev: Disable AER for Titan Ridge 4C 2018 To: Atharva Tiwari Cc: Bjorn Helgaas , Lukas Wunner , Kuppuswamy Sathyanarayanan , Feng Tang , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260106182025.1398-1-atharvatiwarilinuxdev@gmail.com> Content-Language: en-US From: Dave Jiang In-Reply-To: <20260106182025.1398-1-atharvatiwarilinuxdev@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 1/6/26 11:20 AM, Atharva Tiwari wrote: > Disable AER for Intel Titan Ridge 4C 2018 > (used in T2 iMacs, where the warnings appear) > that generates continuous pcieport warnings. such as: > > pcieport 0000:00:1c.4: AER: Correctable error message received from 0000:07:00.0 > pcieport 0000:07:00.0: PCIe Bus Error: severity=Correctable, type=Data Link Layer, (Receiver ID) > pcieport 0000:07:00.0: device [8086:15ea] error status/mask=00000080/00002000 > pcieport 0000:07:00.0: [ 7] BadDLLP > > (see: https://bugzilla.kernel.org/show_bug.cgi?id=220651) > > macOS also disables AER for Thunderbolt devices and controllers in their drivers. > > Signed-off-by: Atharva Tiwari > --- > drivers/pci/pcie/portdrv.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c > index 38a41ccf79b9..5330a679fcff 100644 > --- a/drivers/pci/pcie/portdrv.c > +++ b/drivers/pci/pcie/portdrv.c > @@ -240,7 +240,9 @@ static int get_port_device_capability(struct pci_dev *dev) > if ((pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || > pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC) && > dev->aer_cap && pci_aer_available() && > - (pcie_ports_native || host->native_aer)) > + (pcie_ports_native || host->native_aer) && > + !(dev->vendor == PCI_VENDOR_ID_INTEL && > + (dev->device >= 0x15EA && dev->device <= 0x15EC))) You probably want to do this as a PCI quirk rather than adding a vendor specific line in a generic function. See drivers/pci/quirks.c. DJ > services |= PCIE_PORT_SERVICE_AER; > #endif >