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Fri, 26 Sep 2025 02:41:16 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHuz5klMcIvb3MrZNi4OCbe3f77NecmpBgpEJ6NFqmrwZg1RuNb9Z/s7sKtMM9LiBIcoSu0yw== X-Received: by 2002:a05:6a21:6d95:b0:262:d265:a3c with SMTP id adf61e73a8af0-2e7ceeee4a2mr8883796637.32.1758879676491; Fri, 26 Sep 2025 02:41:16 -0700 (PDT) Received: from [10.217.216.188] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b57c559fd56sm4251511a12.38.2025.09.26.02.41.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 26 Sep 2025 02:41:16 -0700 (PDT) Message-ID: <8b74581c-9f74-40ef-8fad-7e172dc303d9@oss.qualcomm.com> Date: Fri, 26 Sep 2025 15:11:10 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] clk: qcom: gcc: Update the SDCC clock to use shared_floor_ops To: Dmitry Baryshkov Cc: Konrad Dybcio , Bjorn Andersson , Michael Turquette , Stephen Boyd , Dmitry Baryshkov , Taniya Das , Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250804-sdcc_rcg2_shared_ops-v1-1-41f989e8cbb1@oss.qualcomm.com> <7c1bd3d6-159f-4269-a22a-34290f1be0cf@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=I9Vohdgg c=1 sm=1 tr=0 ts=68d65fbe cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=rUtaezTdWwXcHsiEHkoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: LkXXbapwQ0sxYWPk8zKWmK_NnnTUqzVB X-Proofpoint-ORIG-GUID: LkXXbapwQ0sxYWPk8zKWmK_NnnTUqzVB X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTI1MDE3MSBTYWx0ZWRfX5xGQxmlSqwxh yU5NUpSyBZxpSsro0VOyoQZTUODtNrKUiHq1SyRW/F0KgVzyly+xT7NedGvrxBzfd0nXk+48I5J hbzfQri/r/MR862nBpLO//m19d4fULKN9/DYhPAFPTmdqYiJvtVRlkC3vejUgnk03xSjFPkYUqJ /SjWKNBz6UK0hTDWKaJvBdRlFiV9mXMNay2WEBG/WAfiv8AkfJdKQYlOfQ7HaNtVjF14TmCzDgQ 12UTRBKWJxdnGI2qNLYZjqUWMhko8RD2e9ntWmOvMBoGfv/y1WJ6hn8ochrrCfDxyyMe+iXRBY2 sB/OKlJx1u8jyrTrLjY4gfocV+klIn1fJol3pJDcArGTUjp3mTpd8yuQk/zlfbzl/+gVSHejSiz C/gxXm/I7MpkTWaKiuPWCeQ0EEp9zg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-26_02,2025-09-26_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2509250171 On 8/8/2025 5:48 PM, Dmitry Baryshkov wrote: > On Fri, Aug 08, 2025 at 02:51:50PM +0530, Taniya Das wrote: >> >> >> On 8/7/2025 10:32 PM, Konrad Dybcio wrote: >>> On 8/6/25 11:39 AM, Taniya Das wrote: >>>> >>>> >>>> On 8/6/2025 3:00 PM, Konrad Dybcio wrote: >>>>> On 8/6/25 11:27 AM, Taniya Das wrote: >>>>>> >>>>>> >>>>>> On 8/5/2025 10:52 AM, Dmitry Baryshkov wrote: >>>>>>> On Mon, Aug 04, 2025 at 11:59:21PM +0530, Taniya Das wrote: >>>>>>>> gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" during >>>>>>>> boot. This happens due to the floor_ops tries to update the rcg >>>>>>>> configuration even if the clock is not enabled. >>>>>>> >>>>>>> This has been working for other platforms (I see Milos, SAR2130P, >>>>>>> SM6375, SC8280XP, SM8550, SM8650 using shared ops, all other platforms >>>>>>> seem to use non-shared ops). What's the difference? Should we switch all >>>>>>> platforms? Is it related to the hypervisor? >>>>>>> >>>>>> >>>>>> If a set rate is called on a clock before clock enable, the >>>>> >>>>> Is this something we should just fix up the drivers not to do? >>>>> >>>> >>>> I do not think CCF has any such limitation where the clock should be >>>> enabled and then a clock rate should be invoked. We should handle it >>>> gracefully and that is what we have now when the caching capabilities >>>> were added in the code. This has been already in our downstream drivers. >>> >>> Should we do CFG caching on *all* RCGs to avoid having to scratch our >>> heads over which ops to use with each clock individually? >>> >> >> Yes, Konrad, that’s definitely the cleanest approach. If you're okay >> with it, we can proceed with the current change first and then follow up >> with a broader cleanup of the rcg2 ops. As part of that, we can also >> transition the relevant SDCC clock targets to use floor_ops. This way, >> we can avoid the rcg configuration failure logs in the boot sequence on >> QCS615. > > the rcg2_shared_ops have one main usecase - parking of the clock to the > safe source. If it is not required for the SDCC clock, then it is > incorrect to land this patch. Along with the floor functionality we require parking of the clock to safe source for SDCC clock. I am reusing the shared_floor_ops introduced recently for SAR2130P explicitly for SDCC clocks. > > If you are saying that we should be caching CFG value for all clock > controllers, then we should change instead the clk_rcg2_ops. > That is not required for all clock controllers and which ever clock controller's clock requires it we use rcg2_shared_ops which was updated to park the cfg. >> >>>> >>>> We can add the fix to do a check 'clk_hw_is_enabled(hw)' in the normal >>>> rcg2_ops/rcg2_floor/ceil_ops as well, then we can use them. >>> >>> FWIW this is not the first time this issue has popped up.. >>> >>> I don't remember the details other than what I sent in the thread >>> >>> https://lore.kernel.org/linux-arm-msm/20240427-topic-8450sdc2-v1-1-631cbb59e0e5@linaro.org/ >>> >> >> Yes, but as I mentioned the new ops looks much cleaner, so wanted to >> take this approach. >> >>> Konrad >>>> >>>> AFAIK the eMMC framework has this code and this is not limited to drivers. >>>> >>> >> >> -- >> Thanks, >> Taniya Das >> > -- Thanks, Taniya Das