From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDCF9C433ED for ; Thu, 22 Apr 2021 01:18:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8368861435 for ; Thu, 22 Apr 2021 01:18:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239610AbhDVBT2 (ORCPT ); Wed, 21 Apr 2021 21:19:28 -0400 Received: from mga14.intel.com ([192.55.52.115]:22442 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234970AbhDVBT0 (ORCPT ); Wed, 21 Apr 2021 21:19:26 -0400 IronPort-SDR: TayZT3Y70wM/gE5nrSFGpiqHqe5JfvXefU2419e0UWwac69mCskqlcAvQ+o6HMmdJKU6vnDOYJ SGQJamWcsccA== X-IronPort-AV: E=McAfee;i="6200,9189,9961"; a="195363039" X-IronPort-AV: E=Sophos;i="5.82,241,1613462400"; d="scan'208";a="195363039" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2021 18:18:52 -0700 IronPort-SDR: nnmpHPoD1JWEAFnLt2mNlW4tqI85WpxTTu5jISRn6lWir05mjwaI3ahzszhVSAkmloK+eV5AfG 97q0Vm2FOYIQ== X-IronPort-AV: E=Sophos;i="5.82,241,1613462400"; d="scan'208";a="427730533" Received: from likexu-mobl1.ccr.corp.intel.com (HELO [10.255.29.162]) ([10.255.29.162]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2021 18:18:49 -0700 Subject: Re: [PATCH RESEND 1/2] perf/x86: Skip checking MSR for MSR 0x0 To: Sean Christopherson Cc: Peter Zijlstra , Kan Liang , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Thomas Gleixner , Borislav Petkov , x86@kernel.org, linux-kernel@vger.kernel.org References: <20210421021825.37872-1-like.xu@linux.intel.com> From: Like Xu Organization: Intel OTC Message-ID: <8b799e26-f8b0-adeb-b8a6-331087c0d4be@linux.intel.com> Date: Thu, 22 Apr 2021 09:18:47 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.9.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2021/4/21 23:30, Sean Christopherson wrote: > On Wed, Apr 21, 2021, Like Xu wrote: >> The Architecture LBR does not have MSR_LBR_TOS (0x000001c9). >> When ARCH_LBR we don't set lbr_tos, the failure from the >> check_msr() against MSR 0x000 will make x86_pmu.lbr_nr = 0, >> thereby preventing the initialization of the guest LBR. >> >> Fixes: 47125db27e47 ("perf/x86/intel/lbr: Support Architectural LBR") >> Signed-off-by: Like Xu >> Reviewed-by: Kan Liang >> --- >> arch/x86/events/intel/core.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c >> index 5272f349dca2..5036496caa60 100644 >> --- a/arch/x86/events/intel/core.c >> +++ b/arch/x86/events/intel/core.c >> @@ -4751,10 +4751,10 @@ static bool check_msr(unsigned long msr, u64 mask) >> u64 val_old, val_new, val_tmp; >> >> /* >> - * Disable the check for real HW, so we don't >> + * Disable the check for real HW or non-sense msr, so we don't > > I think this should be "undefined MSR" or something along those lines. MSR 0x0 > is a "real" MSR, on Intel CPUs it's an alias for IA32_MC0_ADDR; at least it's > supposed to be, most/all Intel CPUs incorrectly alias it to IA32_MC0_CTL. Thank you, Sean. -0 [000] dN.. 38980.032347: read_msr: 0, value fff Do we have a historic story or specification for this kind of alias ? #define MSR_IA32_MC0_ADDR 0x00000402 #define MSR_IA32_MC0_CTL 0x00000400 > > Anyways, my point is that if your definition of "nonsense" is any MSR that is > not a valid perf MSR, then this check is woefully incompletely. If your > definition is a nonsensical value, then this comment is simply wrong. > > What you're really looking for is precisely the case where the MSR was zero > initialized and never defined. > >> * mess with potentionaly enabled registers: >> */ >> - if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) >> + if (!boot_cpu_has(X86_FEATURE_HYPERVISOR) || !msr) >> return true; >> >> /* >> -- >> 2.30.2 >>