From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751702AbeBZVWA (ORCPT ); Mon, 26 Feb 2018 16:22:00 -0500 Received: from mail-cys01nam02on0066.outbound.protection.outlook.com ([104.47.37.66]:2624 "EHLO NAM02-CY1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751608AbeBZVVy (ORCPT ); Mon, 26 Feb 2018 16:21:54 -0500 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=andrew.cooks@opengear.com; Subject: Re: [RESEND][PATCH v4 1/3] i2c: piix4: Fix port selection for AMD Family 16h Model 30h To: "Tobin C. Harding" Cc: Jean Delvare , Wolfram Sang , "open list:I2C/SMBUS CONTROLLER DRIVERS FOR PC" , open list , Andrew Cooks , linux-acpi@vger.kernel.org, platypus-sw@opengear.com References: <20180226085837.GA15131@eros> From: Andrew Cooks Message-ID: <8b8638e2-18a2-5865-4e7a-27092b053b1b@opengear.com> Date: Tue, 27 Feb 2018 07:21:37 +1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <20180226085837.GA15131@eros> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [59.167.150.161] X-ClientProxiedBy: MEAPR01CA0048.ausprd01.prod.outlook.com (52.134.192.36) To DM5PR15MB1211.namprd15.prod.outlook.com (10.173.209.17) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c65eec69-142c-4bf8-5eaf-08d57d5ef456 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(7020095)(4652020)(5600026)(4604075)(2017052603307)(7153060)(7193020);SRVR:DM5PR15MB1211; X-Microsoft-Exchange-Diagnostics: 1;DM5PR15MB1211;3:ihWHFmnmdYBmWbmzAIEw8H49/GBEps7w0lVtb0Vf5oFbNq6v4J2KIp3ONfd8a5iKqYw4FMK08VOVXQMYSkhxCigEsoaZjOy24dk5MivVygvIeowsjmxvu3rJB+B8ndz7Y0KeIeFjYMRFQxnT4QFapinePUllq1zABlWcFoTbne40wCAjfuwrU/oh9XyXUAdBPafX4k1gBS41d4s1EfQoPqroFreBOHJf0KPoofm4EC0Sl3porNTt83Dq7c7BbJLs;25:3gwbOIC5KGRfEPFqKw1kQKx7zYZTYg2gRQ8NlYt5mcpsgvkpLluAW8FzNCOwp2R915oYhj+vtScpNh5pBng13rW29VmWax6CWR9qMGGqOQfoolTBPRFm+2N92OtfyUkp55qNt1oCKpAlR+x2xA3Bm4UPyPNOs2T+kdbqMmuuJgIJcrfekc1V/035PIqvCB6Z2uJAQxcLOUxfFizXFC75MmB5dQ5th1t6N08XxCoPg34ICuh40gY2jDuX7iLckpbPyYjWZnM2z15pOjz68Z72Yd6gO60zLG+U19kXI02mh7g4/wsVkyunKCPV+7mm9VzqoRLkFdyHR4fbHP7wHo6BbQ==;31:eWkE/5huu80a3COELC7HHnETnTV/BBRqMsk4sZ6bXAROnc3jrskznJVyAxcb92BUZkP9LUE5ykVctiDSR0PhnfTawPVn+DmpLnabVzhrWrunpQ7hCzN/Kimr0MZZ4+cQt0RxTfHQR4BbiW0Mne6+GCNGa+Zibdq0L2F/r0kChh6xCxxFcc8QcfTAUoIXDs5zzw4A1HIFjgoaPDOSHHhI97Vma+9n2P7QsFto/Y4KIeE= X-MS-TrafficTypeDiagnostic: DM5PR15MB1211: X-Microsoft-Exchange-Diagnostics: 1;DM5PR15MB1211;20:IZcdR2JSVYE0+9AWmVlwYjQbuH3Tf1RC5VYzq5Vk2bIfv3cC/3NDDGAzwfkFZfuqJE2gJdguXHqBasdehnRIEu+yq4OOj9Aq6KsEiR+itlfBfIMy/HyEun8UeKJ3LibEEOoCinqjI+0va39fyGvnlZ0jU82XAaLpLic9bKyfuoI=;4:PB/uyvB6pletbE3jxT9/MiRs1Q2pYCtqoQkA3Mwew/IQ+uBNZ9F6wRskkKgI3AVAJajYRqAIstfF3wH9WQBq1g4kp5Wz0k0Ixj6O87dfIwYqlB9ciIMIWH5a+5YiFpRGgz9nij5xGRtys18LFyIPAurabAhwVuaynKNy13SI4ub9G0oIQAFlkA/WC9MApnhwjcsI2+yNnRBPsBsHdfJF/+aiSbA2VQD3B4GcVFF8vv1icvMDDF9xiz/N8MoH2zjgg9IkdcsKWSZNzunlUoGDaA== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; 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Harding wrote: > On Mon, Feb 26, 2018 at 10:28:43AM +1000, Andrew Cooks wrote: >> Family 16h Model 30h SMBus controller needs the same port selection fix >> as described and fixed in commit 0fe16195f891 ("i2c: piix4: Fix SMBus port >> selection for AMD Family 17h chips") >> >> commit 6befa3fde65f ("i2c: piix4: Support alternative port selection >> register") also fixed the port selection for Hudson2, but unfortunately >> this is not the exact same device and the AMD naming and PCI Device IDs >> aren't particularly helpful here. >> >> The SMBus port selection register is common to the following Families >> and models, as documented in AMD's publicly available BIOS and Kernel >> Developer Guides: >> >> 50742 - Family 15h Model 60h-6Fh (PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) >> 55072 - Family 15h Model 70h-7Fh (PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) >> 52740 - Family 16h Model 30h-3Fh (PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) >> >> The Hudson2 PCI Device ID (PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) is shared >> between Bolton FCH and Family 16h Model 30h, but the location of the >> SmBus0Sel port selection bits are different: >> >> 51192 - Bolton Register Reference Guide >> >> We distinguish between Bolton and Family 16h Model 30h using the PCI >> Revision ID: >> >> Bolton is device 0x780b, revision 0x15 >> Family 16h Model 30h is device 0x780b, revision 0x1F >> Family 15h Model 60h and 70h are both device 0x790b, revision 0x4A. >> >> The following additional public AMD BKDG documents were checked and do >> not share the same port selection register: >> >> 42301 - Family 15h Model 00h-0Fh doesn't mention any >> 42300 - Family 15h Model 10h-1Fh doesn't mention any >> 49125 - Family 15h Model 30h-3Fh doesn't mention any >> >> 48751 - Family 16h Model 00h-0Fh uses the previously supported >> index register SB800_PIIX4_PORT_IDX_ALT at 0x2e >> >> Signed-off-by: Andrew Cooks >> --- >> drivers/i2c/busses/i2c-piix4.c | 12 +++++------- >> 1 file changed, 5 insertions(+), 7 deletions(-) >> >> diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c >> index 174579d..5c90a44 100644 >> --- a/drivers/i2c/busses/i2c-piix4.c >> +++ b/drivers/i2c/busses/i2c-piix4.c >> @@ -99,7 +99,7 @@ >> #define SB800_PIIX4_PORT_IDX_MASK 0x06 >> #define SB800_PIIX4_PORT_IDX_SHIFT 1 >> >> -/* On kerncz, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */ >> +/* On kerncz and Hudson2, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */ >> #define SB800_PIIX4_PORT_IDX_KERNCZ 0x02 >> #define SB800_PIIX4_PORT_IDX_MASK_KERNCZ 0x18 >> #define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ 3 >> @@ -359,18 +359,16 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, >> >> /* Find which register is used for port selection */ >> if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD) { >> - switch (PIIX4_dev->device) { >> - case PCI_DEVICE_ID_AMD_KERNCZ_SMBUS: >> + if ((PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) || > > nit: if (PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS || > >> + (PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS && >> + PIIX4_dev->revision >= 0x1F)) { > > > Hope this helps, It does, thanks. I'll roll this fix in with whatever other feedback I get before sending the next patch version. a.