From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-m15599.qiye.163.com (mail-m15599.qiye.163.com [101.71.155.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71F301E4BE for ; Mon, 27 Apr 2026 01:58:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=101.71.155.99 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777255091; cv=none; b=osAu4Q4RqodWvJif8ULp9GRfiTaEkH/FxxYGHZNii3iVYsbAerjjYehFD7ev0xU831LwZlUEaziYaWZQ/J3Q7SPSLoheG1rYHOnqfjgxWA3ylVL4MEaMc4bOVQVRnRoNXVvOUV9zKRdr+H9PIqrLHzgMmHt1QiyNXscSwgC9mC4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777255091; c=relaxed/simple; bh=1d8l61NQGpTgnU9G+8vJXaX23oXSUFBSOl8jWN/sPTA=; h=Message-ID:Date:MIME-Version:Cc:Subject:To:References:From: In-Reply-To:Content-Type; b=eGiqmL6yn0/kHQHbS3kLdfiz53j279/wxZiCbkITahtIqYYXkbhb4Dv67D6PbVkWBL0cmmWMeCZHdueUE2wjEbmQg2QpcVdpl8hf624PXGFlzK2Tqo7mNWBT/o0N9NuD52p4+s/bpoYhxWfOT4MLOlUXll7LukeBhVVsqbDw5CE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=IjSoo2P0; arc=none smtp.client-ip=101.71.155.99 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="IjSoo2P0" Received: from [172.16.12.17] (unknown [61.154.14.86]) by smtp.qiye.163.com (Hmail) with ESMTP id 3c3314299; Mon, 27 Apr 2026 08:42:18 +0800 (GMT+08:00) Message-ID: <8b8ea5e8-4e1a-41e7-b377-0a4246609cf4@rock-chips.com> Date: Mon, 27 Apr 2026 08:42:16 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Cc: shawn.lin@rock-chips.com, linux-rockchip@lists.infradead.org, Heiko Stuebner , Neil Armstrong , linux-kernel@vger.kernel.org Subject: Re: [PATCH] phy: rockchip: naneng-combphy: Fix TX detect RX termination errata To: Vinod Koul , linux-phy@lists.infradead.org References: <1774423383-36599-1-git-send-email-shawn.lin@rock-chips.com> From: Shawn Lin In-Reply-To: <1774423383-36599-1-git-send-email-shawn.lin@rock-chips.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-HM-Tid: 0a9dcc63143c09cckunmc5962bd51746c4 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWRgWCB1ZQUpXWS1ZQUlXWQ8JGhUIEh9ZQVlCHkpKVkweGh9LGEpKSh8fS1YVFA kWGhdVEwETFhoSFyQUDg9ZV1kYEgtZQVlNSlVKTk9VSk9VQ01ZV1kWGg8SFR0UWUFZT0tIVUpLSU 9PT0hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=IjSoo2P0FJMHK5MMBUpKSypXR5a7rsvOxpIZmjilqnCPppzaDlEiEnBbJbfk1AEDCEVyqAlY2QkIpJMDEs4dEMUgqtSrCXN2sDqlya/nXN42m+uu5Q1UgpM3OI89eYqZkSJQ1HEAQUp1YHWyvEIzZi+oSd95GnWwRwCi6YqNWmo=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=3HoksNeI6ZtKSz9ycILX9bag3CMDi7LUrvjdbGKG7Jc=; h=date:mime-version:subject:message-id:from; Ping... 在 2026/03/25 星期三 15:23, Shawn Lin 写道: > Some PHY revisions may fail to detect the peer RX's termination > resistor (RTERM) under certain critical temperature conditions. > This causes TX detection failures on PCIe links. > > Add a workaround to force the RTERM detection ready signal for > affected PHY revisions. This ensures reliable TX-to-RX termination > detection across all operating temperature ranges. > > The fix applies to RK3562, RK3568, RK3576 and RK3588 SoCs which share > the same PHY IP with this hardware errata. > > Signed-off-by: Shawn Lin > --- > > drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c > index b60d6bf..76d4994 100644 > --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c > +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c > @@ -106,6 +106,9 @@ > #define RK3568_PHYREG18 0x44 > #define RK3568_PHYREG18_PLL_LOOP 0x32 > > +#define RK3568_PHYREG26 0x64 > +#define RK3568_PHYREG26_FORCE_RTERM_DET_RDY BIT(5) > + > #define RK3568_PHYREG30 0x74 > #define RK3568_PHYREG30_GATE_TX_PCK_SEL BIT(7) > #define RK3568_PHYREG30_GATE_TX_PCK_DLY_PLL_OFF BIT(7) > @@ -193,6 +196,7 @@ struct rockchip_combphy_cfg { > unsigned int num_phys; > unsigned int phy_ids[3]; > const struct rockchip_combphy_grfcfg *grfcfg; > + bool force_rxterm_det_rdy; > int (*combphy_cfg)(struct rockchip_combphy_priv *priv); > }; > > @@ -264,6 +268,17 @@ static int rockchip_combphy_init(struct phy *phy) > > switch (priv->type) { > case PHY_TYPE_PCIE: > + /* > + * Hardware Errata: TX fails to detect peer RX termination. > + * Some PHY revisions may fail to detect remote RX's RTERM > + * (receiver termination resistor) under certain critical > + * temperature conditions. Set force rterm detect ready to > + * fix it. > + */ > + if (priv->cfg->force_rxterm_det_rdy) > + rockchip_combphy_updatel(priv, RK3568_PHYREG26_FORCE_RTERM_DET_RDY, > + RK3568_PHYREG26_FORCE_RTERM_DET_RDY, RK3568_PHYREG26); > + fallthrough; > case PHY_TYPE_USB3: > case PHY_TYPE_SATA: > case PHY_TYPE_SGMII: > @@ -745,6 +760,7 @@ static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = { > }, > .grfcfg = &rk3562_combphy_grfcfgs, > .combphy_cfg = rk3562_combphy_cfg, > + .force_rxterm_det_rdy = true, > }; > > static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) > @@ -962,6 +978,7 @@ static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { > }, > .grfcfg = &rk3568_combphy_grfcfgs, > .combphy_cfg = rk3568_combphy_cfg, > + .force_rxterm_det_rdy = true, > }; > > static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv) > @@ -1231,6 +1248,7 @@ static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = { > }, > .grfcfg = &rk3576_combphy_grfcfgs, > .combphy_cfg = rk3576_combphy_cfg, > + .force_rxterm_det_rdy = true, > }; > > static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) > @@ -1418,6 +1436,7 @@ static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { > }, > .grfcfg = &rk3588_combphy_grfcfgs, > .combphy_cfg = rk3588_combphy_cfg, > + .force_rxterm_det_rdy = true, > }; > > static const struct of_device_id rockchip_combphy_of_match[] = {