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Fri, 29 May 2026 02:23:26 -0700 (PDT) X-Received: by 2002:a05:6a00:1742:b0:81f:9b4c:81c0 with SMTP id d2e1a72fcca58-84212d2ca6cmr2156359b3a.41.1780046605769; Fri, 29 May 2026 02:23:25 -0700 (PDT) Received: from [192.168.1.2] ([117.192.250.176]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84214affe29sm1240298b3a.3.2026.05.29.02.23.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 29 May 2026 02:23:25 -0700 (PDT) Message-ID: <8b911846-1001-4c20-908d-1384cc81e30b@oss.qualcomm.com> Date: Fri, 29 May 2026 14:52:39 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/5] clk: qcom: gcc-qcm2290: Drop modelling of critical clocks To: Dmitry Baryshkov Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Loic Poulain , Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260528-shikra-dispcc-gpucc-v2-0-953f246a0fbb@oss.qualcomm.com> <20260528-shikra-dispcc-gpucc-v2-1-953f246a0fbb@oss.qualcomm.com> Content-Language: en-US From: Imran Shaik In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI5MDA5MiBTYWx0ZWRfX3tet7taB/wr0 Z6cfWKaVOlMNM3G5+lXk+pX6NESJl0ePhIPheXV+888JlmsZ712q77j5QnkIJagFtumuBG+oSz0 BJKU2cjhB7uZWqb/JuS9Jre0CI5RQpcKAzJVJJNIZtxxn+NrsGggQ8/G4BRNHXuwzKBY7G8J24v d8z1h8KPt7blH89SRth5Cs4UepHCTEN0gYiEaDmdlpuF0uuqMvaSDJxftMZvUV9NGsr8YJGogE3 98MXySRjuqztYapUAucP1DyOa178ILmQ6Ba3+Dz0DbMMHjPTx1hGz3a79Nz3AYvXEFZg0wv/XKi uftmf08OPwSXN5cVcNqeKq8iQAfabADjqPgpCF2w90jJjB/ayer1dWTFSlxQofG9tZTXFFdMJCx HDKpQWmIOV+tkacbXIYuFQjslH7PaFPybMy4i+kOZ1y5zJnsBfs7hloIiv0YBQjc48nSvp2fM/u bIH68tky43c/8dID1VA== X-Authority-Analysis: v=2.4 cv=SNBykuvH c=1 sm=1 tr=0 ts=6a195b0f cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=MYhr4v4WboA43l5+MyccHQ==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=RHQwGL2yU_3FcdO5I0oA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-ORIG-GUID: m2Ql0_FJwGm6usFnqnUXZ_kU4OFC33Xc X-Proofpoint-GUID: m2Ql0_FJwGm6usFnqnUXZ_kU4OFC33Xc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-29_02,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 malwarescore=0 spamscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605290092 On 28-05-2026 06:52 pm, Dmitry Baryshkov wrote: > On Thu, May 28, 2026 at 03:37:02PM +0530, Imran Shaik wrote: >> Drop the modelling of critical GCC clocks on QCM2290 SoC, and keep them >> enabled from probe as per the latest convention. This helps to drop the >> pm_clk handling in QCM2290 GPUCC driver, and the same can be re-used for >> Shikra SoC. >> >> Signed-off-by: Imran Shaik >> --- >> drivers/clk/qcom/gcc-qcm2290.c | 153 +++-------------------------------------- >> 1 file changed, 11 insertions(+), 142 deletions(-) >> >> @@ -2012,19 +1936,6 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = { >> }, >> }; >> >> -static struct clk_branch gcc_gpu_iref_clk = { >> - .halt_reg = 0x36100, >> - .halt_check = BRANCH_HALT_DELAY, >> - .clkr = { >> - .enable_reg = 0x36100, >> - .enable_mask = BIT(0), >> - .hw.init = &(struct clk_init_data){ >> - .name = "gcc_gpu_iref_clk", >> - .ops = &clk_branch2_ops, >> - }, >> - }, >> -}; > > This clock is not critical. Why is it being dropped? > >> - >> static struct clk_branch gcc_gpu_memnoc_gfx_clk = { >> .halt_reg = 0x3600c, >> .halt_check = BRANCH_VOTED, >> @@ -2605,21 +2500,6 @@ static struct clk_branch gcc_venus_ctl_axi_clk = { >> }, >> }; >> >> -static struct clk_branch gcc_video_ahb_clk = { >> - .halt_reg = 0x17004, >> - .halt_check = BRANCH_HALT, >> - .hwcg_reg = 0x17004, >> - .hwcg_bit = 1, >> - .clkr = { >> - .enable_reg = 0x17004, >> - .enable_mask = BIT(0), >> - .hw.init = &(struct clk_init_data){ >> - .name = "gcc_video_ahb_clk", >> - .ops = &clk_branch2_ops, > > This clock isn't marked as CRITICAL, why is it being dropped? > >> - }, >> - }, >> -}; >> - >> static struct clk_branch gcc_video_axi0_clk = { >> .halt_reg = 0x1701c, >> .halt_check = BRANCH_HALT, >> @@ -2686,19 +2566,6 @@ static struct clk_branch gcc_video_venus_ctl_clk = { >> }, >> }; >> >> -static struct clk_branch gcc_video_xo_clk = { >> - .halt_reg = 0x17024, >> - .halt_check = BRANCH_HALT, >> - .clkr = { >> - .enable_reg = 0x17024, >> - .enable_mask = BIT(0), >> - .hw.init = &(struct clk_init_data){ >> - .name = "gcc_video_xo_clk", >> - .ops = &clk_branch2_ops, > > This clock isn't marked as CRITICAL, why is it being dropped? > The above clocks also should have been marked as CRITICAL. Not sure why those are not marked in the QCM2290. Since we are updating the critical clock set, moving all the required clocks to the critical list in line with the latest conventions. >> - }, >> - }, >> -}; >> - >> static struct gdsc gcc_camss_top_gdsc = { >> .gdscr = 0x58004, >> .pd = { >> @@ -2990,6 +2848,17 @@ static int gcc_qcm2290_probe(struct platform_device *pdev) >> if (ret) >> return ret; >> >> + /* Keep some clocks always-on */ >> + qcom_branch_set_clk_en(regmap, 0x17008); /* GCC_CAMERA_AHB_CLK */ >> + qcom_branch_set_clk_en(regmap, 0x17028); /* GCC_CAMERA_XO_CLK */ >> + qcom_branch_set_clk_en(regmap, 0x1700c); /* GCC_DISP_AHB_CLK */ >> + qcom_branch_set_clk_en(regmap, 0x1702c); /* GCC_DISP_XO_CLK */ >> + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_GPU_CFG_AHB_CLK */ >> + qcom_branch_set_clk_en(regmap, 0x36100); /* GCC_GPU_IREF_CLK */ >> + qcom_branch_set_clk_en(regmap, 0x79004); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ >> + qcom_branch_set_clk_en(regmap, 0x17004); /* GCC_VIDEO_AHB_CLK */ >> + qcom_branch_set_clk_en(regmap, 0x17024); /* GCC_VIDEO_XO_CLK */ > > If you are chancing the driver, why are you not using .clk_cbcrs? > Sure, will add these to .clk_cbcrs in next series. Thanks, Imran >> + >> clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config); >> clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config); >> clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config); >> >> -- >> 2.34.1 >> >