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Fri, 13 Nov 2026 17:45:34 -0800 (PST) Received: from [192.168.29.63] ([49.43.231.124]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1b5031918c7sm15907935c88.9.2026.11.13.17.45.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Nov 2026 17:45:33 -0800 (PST) Message-ID: <8b9d14a7-47cf-4020-a5cd-9d17d559170c@oss.qualcomm.com> Date: Sat, 14 Nov 2026 07:15:28 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] dt-bindings: connector: Add PCIe M.2 Mechanical Key B connector To: Rob Herring Cc: Manivannan Sadhasivam , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Bjorn Andersson , Konrad Dybcio , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org References: <20261021-pcie6_fix-v1-0-ad37134c35a3@oss.qualcomm.com> <20261021-pcie6_fix-v1-1-ad37134c35a3@oss.qualcomm.com> <20261030174429.GA781972-robh@kernel.org> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <20261030174429.GA781972-robh@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: esMq18dRIqNMmzmj09Owm9cOsJ2nGayk X-Authority-Analysis: v=2.4 cv=RbcFmFtv c=1 sm=1 tr=0 ts=6af7bd3f cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=OgdsqUoHhxF4GfobPiU6/w==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=MaBVSKTy7IHi2HvaTlUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTE0MDAwNiBTYWx0ZWRfX3gCCfDR5+fcf bBoYRxqFexvXE6uIKjo5XIum0SoV+xeotXN81ABLvF+1PoYjgBfSr/psndnWAAjfvqNRWpf1yjt XbwTil2rkv+2KCSQ8gURBKuosbGEz8X66PGSvpl2FDWS0edtAAUOnFfjiJJ4AFHnGzHb3/F60m9 juP13TkOD8wy+YD0IBsCud8fEEdngBZp0mne34q2LqKYvEw9Ev0YWWGBCTFSyBJigAcgD2GvH3K o8fvsV5X8I4mMkv1FvbI/TehRdPoGPm5CCfMvPnHrfeEDF32wPIXkbs12lFaRY+CfK6YqYBzSFm iZGzm4YdgLDxHyLQWWfwsSswK88/95jU7pe7d6FBuO7wz/zzXcNi9MHSlXooYWJXDP+zIpLnywr Xvvk6L0ewqYLQQu5gnahdz2s8lRZCO+ES4NeOdJGOmZocuC6O1/+hcM6VHK2kTULMQLgBihooiS 4d7wc0ArY40ZpGSf+gg== X-Proofpoint-ORIG-GUID: esMq18dRIqNMmzmj09Owm9cOsJ2nGayk X-Proofpoint-Spam-Info: AW1haW4tMjYxMTE0MDAwNiBTYWx0ZWRfXwuBKKY+/nYWs ljs8iZky/IQTVJSisPcwuvsR9b7dKUHA5vZk8/QrHc1GTP+M1n7Fx7t99Rgj7fp/uN6cSpGB9SE 3myT6mOTQmx8wMcDTYQqyZe2l2Iccgc= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-13_07,2026-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 phishscore=0 adultscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611140006 On 10/30/2026 11:14 PM, Rob Herring wrote: > On Wed, Oct 21, 2026 at 07:21:22PM +0530, Krishna Chaitanya Chundru wrote: >> Add the devicetree binding for PCIe M.2 Mechanical Key B connector >> defined in the PCI Express M.2 Specification, r4.2, sec 3.2.19.1. This >> connector is used to attach WWAN Adapters to the host machine over >> interfaces such as PCIe, USB3.1 Gen1, SSIC, or USB 2.0, selected by the >> Adapter's configuration pins. >> >> The connector provides a primary power supply of 3.3V/VBAT, along with >> optional GPIO signals for WWAN-specific power/radio control: >> FULL_CARD_POWER_OFF#, RESET#, W_DISABLE1#/2#, WAKE_ON_WWAN#, and DPR. >> >> Signed-off-by: Krishna Chaitanya Chundru >> --- >> .../bindings/connector/pcie-m2-b-connector.yaml | 146 +++++++++++++++++++++ >> MAINTAINERS | 1 + >> 2 files changed, 147 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/connector/pcie-m2-b-connector.yaml b/Documentation/devicetree/bindings/connector/pcie-m2-b-connector.yaml >> new file mode 100644 >> index 000000000000..a7f4bcbc5119 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/connector/pcie-m2-b-connector.yaml >> @@ -0,0 +1,146 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/connector/pcie-m2-b-connector.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: PCIe M.2 Mechanical Key B Connector >> + >> +maintainers: >> + - Krishna Chaitanya Chundru >> + >> +description: >> + A PCIe M.2 B connector node represents a physical PCIe M.2 Mechanical Key B >> + connector. Mechanical Key B connectors are used to connect WWAN devices to >> + the host machine over interfaces like PCIe, USB3.1 Gen1, SSIC, or USB 2.0, >> + selected by the Adapter's configuration pins. >> + >> +properties: >> + compatible: >> + const: pcie-m2-b-connector >> + >> + vpcie3v3-supply: >> + description: A phandle to the regulator for the 3.3v/VBAT supply. >> + >> + full-card-power-off-gpios: >> + description: GPIO output to FULL_CARD_POWER_OFF# signal. This signal is >> + used by the host system to turn off the entire Adapter. Refer, PCI >> + Express M.2 Specification r4.0, sec 3.2.13.1 for more details. >> + maxItems: 1 >> + >> + reset-gpios: >> + description: GPIO output to RESET# signal. This signal is used by the >> + host system to place the WWAN Adapter into a power-on reset condition. >> + Refer, PCI Express M.2 Specification r4.0, sec 3.2.13.2 for more >> + details. >> + maxItems: 1 >> + >> + w-disable1-gpios: >> + description: GPIO output to W_DISABLE1# signal. This signal is used by >> + the host system to disable the WWAN radio on the Adapter. Refer, PCI >> + Express M.2 Specification r4.0, sec 3.1.12.3 for more details. >> + maxItems: 1 >> + >> + w-disable2-gpios: >> + description: GPIO output to W_DISABLE2# signal (default function of >> + GPIO_10). This signal is used by the host system to disable a second >> + radio on the Adapter. Refer, PCI Express M.2 Specification r4.0, >> + sec 3.1.12.3 for more details. >> + maxItems: 1 > On the pinouts I find, I only see 0 or 1 w_disable. W_DISABLE1# is pin 8. W_DISABLE2# is GPIO_10 (pin 26), valid in Port Config_0..2 only and absent from the SSD pinouts. It stays optional, and I'll document the dependency. >> + >> + wowwan-gpios: >> + description: GPIO input to WAKE_ON_WWAN# (WoWWAN#) signal. The Adapter >> + asserts this signal to wake up the host system. Refer, PCI Express M.2 >> + Specification r4.0, sec 3.2.13.3.6 for more details. >> + maxItems: 1 > Don't see this on any of them. There is an ALERT# signal.  WoWWAN# is GPIO_11 (pin 23) in Tables 3-21/3-22, Config_0..2 only. ALERT# (pin 44) is the SSD SMBus alert in 3-23/3-24.  I'll keep WoWWAN# optional and add ALERT# separately, since Alexey noted the socket also takes SSDs.+ >> + dpr-gpios: >> + description: GPIO output to the Dynamic Power Reduction (DPR) signal. >> + This signal is provided by a host system proximity sensor to the >> + Adapter to trigger a reduction in the radio transmit output power to >> + meet regulatory SAR requirements. Refer, PCI Express M.2 Specification >> + r4.0, sec 3.2.13.4 for more details. >> + maxItems: 1 >> + >> + clocks: >> + description: 32.768 KHz Suspend Clock (SUSCLK) input from the host system to >> + the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.1 for >> + more details. >> + maxItems: 1 >> + >> + ports: >> + $ref: /schemas/graph.yaml#/properties/ports >> + description: OF graph bindings modeling the interfaces exposed on the >> + connector. Since a single connector can have multiple interfaces, every >> + interface has an assigned OF graph port number as described below. >> + >> + properties: >> + port@0: >> + $ref: /schemas/graph.yaml#/properties/port >> + description: PCIe interface for WWAN >> + >> + port@1: >> + $ref: /schemas/graph.yaml#/properties/port >> + description: SSIC interface for WWAN >> + >> + port@2: >> + $ref: /schemas/graph.yaml#/properties/port >> + description: USB 2.0 interface for WWAN >> + >> + port@3: >> + $ref: /schemas/graph.yaml#/properties/port >> + description: USB3.1 Gen1 interface for WWAN > Port nodes are generally independent. Endpoints are muxed connections. > As SSIC and USB3 are the same pins, they should be the same port. You > could use endpoint numbering to define SSIC vs. USB3.  Agreed. I'll use pin-group ports with endpoints as the alternatives. Should PCIe lane 1 be an endpoint on the 29-37 port,  or should the PCIe port imply link width and leave lane 1 out of the graph? - Krishna Chaitanya. > Rob