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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-658b469e4a9sm8848179a12.27.2026.02.03.02.19.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Feb 2026 02:19:13 -0800 (PST) Message-ID: <8ba352c0-7674-4e94-9cd4-c1327179034e@oss.qualcomm.com> Date: Tue, 3 Feb 2026 11:19:11 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: sm8550: Update EAS properties To: Lukasz Luba , Viresh Kumar , webgeek1234@gmail.com, Xilin Wu Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Viresh Kumar , "Rafael J. Wysocki" , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260128-sm8550-eas-v1-1-fb80615bed5c@gmail.com> <76c24508-bb75-475a-b973-d7ad18c302ce@oss.qualcomm.com> <2ca3a260-d05f-4f2d-bf3f-08b4a3908792@arm.com> <26e2aa8a-912b-4e83-ad00-130cc137aa4b@oss.qualcomm.com> <3f20ae13-a206-4ddc-8556-f929d8727b50@arm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <3f20ae13-a206-4ddc-8556-f929d8727b50@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: eCfaevCHGGb1OmxKs9WuHHXQoz-2wjah X-Authority-Analysis: v=2.4 cv=OrRCCi/t c=1 sm=1 tr=0 ts=6981cba3 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=pGLkceISAAAA:8 a=7CQSdrXTAAAA:8 a=IPjbp5aJMyH78Fb_HP0A:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-GUID: eCfaevCHGGb1OmxKs9WuHHXQoz-2wjah X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjAzMDA4MSBTYWx0ZWRfX5RTrsAR+UkD4 qqgfuYGmbYNCXHv708FxyhlxGSlLi0GAlj5RZ5VFDGUdOEg4fBknDwV3ACaFxZVrKFt3V3ivZUa 42vcpxJbP/WcAP5n2D+SRN4djyOS0jcJ62g2NgWyS31QjYGtuGjNrQMNAZJOZrjs3D+kUdq6OuH VV0LriWTBizy9PnjjlH/t/IpOu+O0kQgGaRqYphiwqA/0G/GNkK/4A3hsss5rl55NtMYIHOmwYK aoJtV5JwI2LstEl0sYhDWQ2fTVZGOdbTHOvD9rAETRCC2Q3o4iS0jZBJdI8KKsY028udcYuge2V x8hnQD8VrvjJWQ0cg9fgW8ZqH7Oevth8o/u2cEAoy/3tRpN3B8X6o7zX+9lEbcenE8wrWeSBqzI MHWepzj4LrkJYmJehpeajz1AftuOPObP4ffuGMsrDs/tC9HiSzVQSj4Nyf89RH+TH18CSLTAIlk R4vBwy/7KzkcrDJyYNw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-03_03,2026-02-02_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 adultscore=0 malwarescore=0 phishscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602030081 On 2/2/26 10:28 AM, Lukasz Luba wrote: > > > On 1/29/26 11:56, Konrad Dybcio wrote: >> On 1/29/26 12:38 PM, Lukasz Luba wrote: >>> >>> >>> On 1/29/26 11:23, Konrad Dybcio wrote: >>>> On 1/29/26 12:05 PM, Viresh Kumar wrote: >>>>> On 29-01-26, 12:00, Konrad Dybcio wrote: >>>>>> On 1/28/26 8:11 PM, Aaron Kling via B4 Relay wrote: >>>>>>> It should be noted that the A715 cores seem less efficient than the >>>>>>> A710 cores. Therefore, an average value has been assigned to them, >>>>>>> considering that the A715 and A710 cores share a single cpufreq >>>>>>> domain. >>>>>> >>>>>> Regarding the CPUFreq domain shared across cores with different power >>>>>> characteristics, I think we shouldn't be lying to the OS, rather Linux >>>>>> should be able to deal with it, somehow. >>>>> >>>>> cpufreq-domain == cpufreq-policy here I guess. All CPUs that change >>>>> their DVFS state together should be part of one policy. Not sure if >>>>> there is something else you were pointing at. >>>> >>>> Yes, they change their state together. >>>> >>>> The question is whether it's okay for these CPUs to have different >>>> dynamic-power-coefficient values, and whether the EM code won't be >>>> thrown off by that. >>> >>> The Energy Model won't support that, since it's a single >>> instance per-cpufreq-policy and we have to pick 'some' values (in this >>> case). >> >> Do you think taking an average, like suggested by the original author, >> makes sense here? >> >>>> Again, they differ because within that shared policy, there's 2 >>>> separate kinds of cores (2x Cortex-A715 + 2x Cortex-A710). >>>> >>> >>> For this SoC I assume the physical HW (power rail and frequency domain) >>> is linked to those 4 CPUs. That's quite novel configuration... >>> >>> Maybe I could give you some hint at least for the EAS part (the EM >>> for EAS), because for something in other areas (e.g. thermal) might >>> be really tough. >> >> In this case, these cores have **fairly** similar power/perf >> characteristics, as evidenced by the measurements in the root of >> this thread, see: >> >> https://lore.kernel.org/linux-arm-msm/20260128-sm8550-eas-v1-1-fb80615bed5c@gmail.com/ >> >>> What are the other CPUs in that SoC and their DVFS configs? >> >> Domain 0: 3x A510 >> Domain 1: 2x A715 + 2x A710 >> Domain 2: 1x X3 >> > > I have analyzed that data both: power and performance > (the 7-zip benchmark). It looks good and might fly upstream. > Although, I wonder if that benchmark truly reflects the > workload for that gaming handheld... FWIW this is the common SoC DT, the author of the patch only happens to have that SoC inside a gaming handheld > For 'normal' usage (mix of stuff running on a device, not > mainly games) these derived numbers are promising. > The plot that I got for the Energy Model shows fairly > similar efficiency for a710 and a715 - which is expected. > There is also a nice size (60%) of an overlapping region to operate > on for the EAS. That would be typical model for day-of-usage > with mixed scenario. > The platform engineers can later modify the EM data in run-time > to better reflect their workload's behavior on the SoC. > > Since this is mainline change for sm8550 and looks - LGTM. > > Reviewed-by: Lukasz Luba Thanks for your insight! Konrad