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Tue, 11 Mar 2025 08:48:56 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 52B8mtut007769 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 11 Mar 2025 08:48:55 GMT Received: from [10.218.22.7] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 11 Mar 2025 01:48:49 -0700 Message-ID: <8bc65a73-876e-4063-8e7a-7a54e6e4c096@quicinc.com> Date: Tue, 11 Mar 2025 14:18:46 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/8] clk: qcom: common: Manage rpm, configure PLLs & AON clks in really probe To: Dmitry Baryshkov CC: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Ajit Pandey , Imran Shaik , "Taniya Das" , Satya Priya Kakitapalli , , , , References: <20250306-videocc-pll-multi-pd-voting-v2-0-0cd00612bc0e@quicinc.com> <20250306-videocc-pll-multi-pd-voting-v2-3-0cd00612bc0e@quicinc.com> Content-Language: en-US From: Jagadeesh Kona In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: akzZagIWj4VqenqHZAUwBEuURKiL2BVv X-Authority-Analysis: v=2.4 cv=fvgmZE4f c=1 sm=1 tr=0 ts=67cff8f8 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=IeHSON8_HjXeqkJcNh0A:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: akzZagIWj4VqenqHZAUwBEuURKiL2BVv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-11_01,2025-03-11_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 mlxlogscore=999 suspectscore=0 phishscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503110059 On 3/7/2025 2:17 PM, Dmitry Baryshkov wrote: > On Thu, Mar 06, 2025 at 02:25:35PM +0530, Jagadeesh Kona wrote: >> Add support for runtime power management, PLL configuration and enabling >> critical clocks in qcom_cc_really_probe() to commonize the clock >> controller probe. > > Please split this into two commits: one for the runtime PM and another > one for clock configuration, because ... > Sure, will split this in the next series. >> >> The runtime power management is not required for all clock controllers, >> hence handle the rpm based on use_rpm flag in clock controller descriptor. >> Also the power domains need to be kept enabled during pll configuration, >> hence attach all required power domains prior to calling get_sync() on the >> device. >> >> Signed-off-by: Jagadeesh Kona >> --- >> drivers/clk/qcom/common.c | 45 ++++++++++++++++++++++++++++++++++++--------- >> drivers/clk/qcom/common.h | 16 ++++++++++++++++ >> 2 files changed, 52 insertions(+), 9 deletions(-) > > [...] > >> + >> + for (i = 0; i < desc->num_plls; i++) >> + qcom_cc_clk_pll_configure(desc->plls[i], regmap); >> + >> + for (i = 0 ; i < desc->num_clks_cfg; i++) >> + regmap_update_bits(regmap, clks_cfg[i].offset, >> + clks_cfg[i].mask, clks_cfg[i].mask); >> + > > ... just calling regmap_update_bits() looks like a step backwards. In > the past several years we got several sensible wrappers and helpers. I > suggest having a callback instead of a fixed 'update bits' table. > Sure, will check and add a callback to handle all these clock config settings. Thanks, Jagadeesh >> reset = &cc->reset; >> reset->rcdev.of_node = dev->of_node; >> reset->rcdev.ops = &qcom_reset_ops; > > The RPM part is fine with me. >