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Wed, 23 Jul 2025 00:03:17 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHOdoj/Z0jEqXcV2S8L/uQoTbevs9LrXwjf85fcxGIO0OJDtv0iwbEYch0xtIVtUG3ntXRiWw== X-Received: by 2002:a05:6a20:72a1:b0:220:7e77:f4f7 with SMTP id adf61e73a8af0-23d4911f9e1mr2982034637.25.1753254197437; Wed, 23 Jul 2025 00:03:17 -0700 (PDT) Received: from [10.151.37.217] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b3f2fe69c80sm8194616a12.12.2025.07.23.00.03.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 23 Jul 2025 00:03:16 -0700 (PDT) Message-ID: <8bea2f87-35fa-4411-acb3-951889b92713@oss.qualcomm.com> Date: Wed, 23 Jul 2025 12:33:12 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] arm64: dts: qcom: ipq5424: Describe the 4-wire UART SE To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250630-ipq5424_hsuart-v3-1-fa0866b12cbc@oss.qualcomm.com> Content-Language: en-US From: Kathiravan Thirumoorthy In-Reply-To: <20250630-ipq5424_hsuart-v3-1-fa0866b12cbc@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 60W1BrnjiYa2152cAObXmQvZQHF_7Ioa X-Authority-Analysis: v=2.4 cv=SYL3duRu c=1 sm=1 tr=0 ts=68808936 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=LH_GineItQtitB-Bug8A:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIzMDA1OCBTYWx0ZWRfX+z70hhXtkrYS ufB1Zgyvg/Am7h8f6dMMzv5jHJuQslm6kpkDbS44ykm3+TbxhI6h67qaDFN11stef3AhFidNOZf 0YZkHBT6wo/X3zoV3GLQ2Qi0VdyxtjOKQ7/Sq5oPokf4d2rWKkDOWhHV2JO4w8lmhO1VIfSG+fL wJFn7a+n5WIvMQes6j4pYK9d1vP5ot9tuzesZ6HmZnvosKXfaL8uwslb5V37Q2fSCBcNJGHdj9K pUQ/jFCA3nFylq7Qs10/ueosTJMPfuX5e8EBOUY94zs4oVQrCAVRLsvaaANyJX09Ek8PlN6Y76N WysxoRbMuWXTznElGVezw2ralvkcamUSu1YqMiDZbPUaWSg9daOwRdwlLcNB2VYES+mq6T4GIDi wr8K5nd6POQ3dEDb2lYVO4GR6xWCN2BHthzLp9d6jalNeRg64wh5UhfqSWzhQcarKEIDxo99 X-Proofpoint-ORIG-GUID: 60W1BrnjiYa2152cAObXmQvZQHF_7Ioa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-23_01,2025-07-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 mlxscore=0 bulkscore=0 mlxlogscore=999 lowpriorityscore=0 phishscore=0 malwarescore=0 spamscore=0 clxscore=1015 priorityscore=1501 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507230058 On 6/30/2025 2:20 PM, Kathiravan Thirumoorthy wrote: > QUPv3 in IPQ5424 consists of six Serial Engines (SEs). Describe the > first SE, which supports a 4-wire UART configuration suitable for > applications such as HS-UART. > > Note that the required initialization for this SE is not handled by the > bootloader. Therefore, add the SE node in the device tree but keep it > disabled. Enable it once Linux gains support for configuring the SE, > allowing to use in relevant RDPs. > > Signed-off-by: Kathiravan Thirumoorthy Gentle Reminder... > --- > Changes in v3: > - Add the pinctrl configuration for the SE (Konrad) > - Link to v2: > https://lore.kernel.org/linux-arm-msm/20250624-ipq5424_hsuart-v2-1-6566dabfe4a6@oss.qualcomm.com/ > Changes in v2: > - Correct the interrupt number > - Link to v1: > https://lore.kernel.org/r/20250624-ipq5424_hsuart-v1-1-a4e71d00fc05@oss.qualcomm.com > --- > arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 12 ++++++++++++ > arch/arm64/boot/dts/qcom/ipq5424.dtsi | 9 +++++++++ > 2 files changed, 21 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts > index 1f89530cb0353898e0ac83e67dfd32721ede88f8..8dee436464cb588fdde707b06bd93302b2499454 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts > +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts > @@ -224,6 +224,13 @@ data-pins { > }; > }; > > + uart0_pins: uart0-default-state { > + pins = "gpio10", "gpio11", "gpio12", "gpio13"; > + function = "uart0"; > + drive-strength = <8>; > + bias-pull-down; > + }; > + > pcie2_default_state: pcie2-default-state { > pins = "gpio31"; > function = "gpio"; > @@ -239,6 +246,11 @@ pcie3_default_state: pcie3-default-state { > }; > }; > > +&uart0 { > + pinctrl-0 = <&uart0_pins>; > + pinctrl-names = "default"; > +}; > + > &uart1 { > pinctrl-0 = <&uart1_pins>; > pinctrl-names = "default"; > diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi > index 66bd2261eb25d79051adddef604c55f5b01e6e8b..2b8499422a8a9a2f63e1af9ae8c189bafe690514 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi > @@ -417,6 +417,15 @@ qupv3: geniqup@1ac0000 { > #address-cells = <2>; > #size-cells = <2>; > > + uart0: serial@1a80000 { > + compatible = "qcom,geni-uart"; > + reg = <0 0x01a80000 0 0x4000>; > + clocks = <&gcc GCC_QUPV3_UART0_CLK>; > + clock-names = "se"; > + interrupts = ; > + status = "disabled"; > + }; > + > uart1: serial@1a84000 { > compatible = "qcom,geni-debug-uart"; > reg = <0 0x01a84000 0 0x4000>; > > --- > base-commit: 1343433ed38923a21425c602e92120a1f1db5f7a > change-id: 20250630-ipq5424_hsuart-0cf24b443abb > > Best regards,