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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: GIQbgF8rg7eENpLaSo/zBCIR31Vs/NnZwsFo1cJoFqc92TUVK8b9XEXsVpQ0toteUD3pCxFIHASAjSAe+IzB1VuSKPwY1SPpVtWPhbgOrxSwdDlaaPybW1J+R9zMeY22IkaQc3tXqo2NbahpFnBtdsBmtudEf1mNq/N3e8PxVzUDpa/lg/yKM75zHaTZT0oQq6aWZTsE47tYgLU2/Yv0GXaorNFQmqoeh22bnn01vPxT6G6g/unUNmvFV88Y5lo7Dx7AX0ZzrIaVQ9ekM1IGRaZXkexfUVoxCBl1bzahGTkd5Qdh2+t+Dp0GtEsdDIRw7Emy/NHJ8ezrWR4jbLoZnJkSn4uA7UETQNPeqoQ+h63ocWPl/Qe8d8y3CfKK4o2tMKu4w/viHA/vaSjvO5ISTIz1siQqp/qPOLrzFxVVvnFqr3ONC8dXBbmmGkdm2x73 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2026 05:42:55.5638 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4e4b8cbb-8df8-4b8c-12ba-08df3bc8ceab X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM3PEPF000265C5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7092 From: Zhi Wang The vGPU manager needs the VMMU segment size and FIFO engine topology returned by a successful GSP boot to divide instance resources. Construct VgpuManager only for a vGPU-enabled boot. Retain the GPU-owned channel pool, the ordered host-driven engine list and the VMMU segment size. Expose the existing decoded VMMU value from GspStaticInfo at its first consumer, preserving zero when firmware omits the key. Keep the runtime values in the manager for its instance module, and drop the manager before the pool and memory resources it borrows. Cc: Alexandre Courbot Signed-off-by: Zhi Wang Signed-off-by: Alok Kumar --- drivers/gpu/nova-core/gpu.rs | 23 ++++++++++++++- drivers/gpu/nova-core/gsp/commands.rs | 5 ++-- drivers/gpu/nova-core/gsp/commands/gmc.rs | 1 + drivers/gpu/nova-core/gsp/fw/commands.rs | 2 +- drivers/gpu/nova-core/vgpu.rs | 36 ++++++++++++++++++++++- 5 files changed, 62 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index 3f8bdbb9a5b2..002c5ba134a6 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -53,7 +53,10 @@ VramAddress, // }, num, - vgpu::VgpuState, // + vgpu::{ + VgpuManager, + VgpuState, // + }, }; #[cfg_attr(not(CONFIG_KUNIT = "y"), expect(dead_code))] @@ -397,6 +400,7 @@ unsafe fn new( #[pin_data] pub(crate) struct Gpu<'gpu> { pub(crate) spec: Spec, + vgpu: Option>, /// GSP event interrupt registration, and the enable of its subtree. /// /// Must be kept declared *before* `gsp_resources`, so that the handler is unregistered, and @@ -534,6 +538,23 @@ pub(crate) fn new<'a>( })?, }), + vgpu: { + let info = &gsp_resources.boot_result.static_info; + match gsp_resources.vgpu_state { + VgpuState::Disabled => None, + VgpuState::Enabled { .. } => Some(VgpuManager::new( + // SAFETY: `chid_pool` is initialized above at its final pinned address. + // The private manager and its pool borrow cannot escape this `Gpu`. + // Completed field drop order drops the manager before the pool; on failure, + // pin-init drops it before the earlier-initialized pool. + unsafe { &*core::ptr::from_ref(chid_pool.as_ref().get_ref()) }, + &info.fifo_engine_list(), + info.vmmu_segment_size, + TOTAL_CHANNELS, + )), + } + }, + _: { irq::gsp::quiesce(tree_ref, &gsp_resources.gsp_falcon); }, diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/gsp/commands.rs index f5ec27995627..799f26e0ae74 100644 --- a/drivers/gpu/nova-core/gsp/commands.rs +++ b/drivers/gpu/nova-core/gsp/commands.rs @@ -11,7 +11,7 @@ use kernel::prelude::*; -use super::fw::commands::FifoEngineList; +pub(crate) use super::fw::commands::FifoEngineList; /// The static GPU configuration, which GSP-RM reports in reply to [`GspInit`](gmc::GspInit). pub struct GspStaticInfo { @@ -25,6 +25,8 @@ pub struct GspStaticInfo { pub(crate) usable_fb_regions: KVec>, /// Exclusive end of the FB physical address space. pub(crate) total_fb_end: u64, + /// VMMU segment size in bytes, or zero if GSP-RM omitted it. + pub(crate) vmmu_segment_size: u64, /// Host-driven engines in firmware FIFO order. fifo_engine_list: FifoEngineList, } @@ -68,7 +70,6 @@ pub fn gpu_short_name(&self) -> core::result::Result<&str, GpuNameError> { } /// Returns the host-driven engines in their firmware FIFO order. - #[expect(dead_code)] pub(crate) fn fifo_engine_list(&self) -> FifoEngineList { self.fifo_engine_list } diff --git a/drivers/gpu/nova-core/gsp/commands/gmc.rs b/drivers/gpu/nova-core/gsp/commands/gmc.rs index c9258ee9e059..6f88c99349ac 100644 --- a/drivers/gpu/nova-core/gsp/commands/gmc.rs +++ b/drivers/gpu/nova-core/gsp/commands/gmc.rs @@ -186,6 +186,7 @@ fn read(payload: &mut SBufferIter>) -> Result, fb_regions: KVVec, bar1_pde_base: u64, - vmmu_segment_size: u64, + pub(crate) vmmu_segment_size: u64, fifo_engine_count: FifoEngineCount, fifo_engine_gmc_ids: [u32; MAX_FIFO_ENGINES], fifo_engine_flags: [u32; MAX_FIFO_ENGINES], diff --git a/drivers/gpu/nova-core/vgpu.rs b/drivers/gpu/nova-core/vgpu.rs index b405ba49c490..5cd82adeb0f8 100644 --- a/drivers/gpu/nova-core/vgpu.rs +++ b/drivers/gpu/nova-core/vgpu.rs @@ -13,7 +13,11 @@ Fsp, VgpuMode, // }, - gpu::Chipset, // + gpu::{ + ChannelIdPool, + Chipset, // + }, + gsp::commands::FifoEngineList, // }; mod hal; @@ -80,3 +84,33 @@ fn query_state( } } } + +/// Runtime resources for an enabled vGPU boot. +pub(crate) struct VgpuManager<'gpu> { + #[expect(dead_code)] + chid_pool: &'gpu ChannelIdPool, + /// VMMU segment size in bytes, or zero if GSP-RM omitted it. + #[expect(dead_code)] + vmmu_segment_size: u64, + #[expect(dead_code)] + total_channels: u32, + #[expect(dead_code)] + fifo_engine_list: FifoEngineList, +} + +impl<'gpu> VgpuManager<'gpu> { + /// Retains runtime parameters from a completed vGPU-enabled GSP boot. + pub(crate) fn new( + chid_pool: &'gpu ChannelIdPool, + fifo_engine_list: &FifoEngineList, + vmmu_segment_size: u64, + total_channels: u32, + ) -> Self { + Self { + chid_pool, + vmmu_segment_size, + total_channels, + fifo_engine_list: *fifo_engine_list, + } + } +} -- 2.53.0