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Tue, 20 May 2025 11:36:02 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: Tfc8a567c59a896e5 Date: Tue, 20 May 2025 16:35:42 +0100 From: "Jiaxun Yang" To: "Gregory CLEMENT" , "Thomas Bogendoerfer" Cc: "Vladimir Kondratiev" , =?UTF-8?Q?Th=C3=A9o_Lebrun?= , "Tawfik Bayouk" , "Thomas Petazzoni" , "linux-mips@vger.kernel.org" , linux-kernel@vger.kernel.org Message-Id: <8c4ef90e-82db-4711-a5f3-446bcca00e9d@app.fastmail.com> In-Reply-To: <20250520-smp_calib-v1-1-cd04f0a78648@bootlin.com> References: <20250520-smp_calib-v1-1-cd04f0a78648@bootlin.com> Subject: Re: [PATCH] MIPS: CPS: Optimise delay CPU calibration for SMP Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable =E5=9C=A82025=E5=B9=B45=E6=9C=8820=E6=97=A5=E5=91=A8=E4=BA=8C =E4=B8=8B=E5= =8D=884:21=EF=BC=8CGregory CLEMENT=E5=86=99=E9=81=93=EF=BC=9A [...] > > This allows to implement calibrate_delay_is_known(), which will return > 0 (triggering calibration) only for the primary CPU of each > cluster. For other CPUs, we can simply reuse the value from their > cluster's primary CPU core. Is __cpu_primary_cluster_mask really necessary? Maybe we can just test if current CPU is the first powered up CPU in the cluster? Thanks Jiaxun > > With the introduction of this patch, a configuration running 32 cores > spread across two clusters sees a significant reduction in boot time > by approximately 600 milliseconds. > > Signed-off-by: Gregory CLEMENT > --- > arch/mips/kernel/smp-cps.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c > index=20 > 02bbd7ecd1b9557003186b9d3d98ae17eac5eb9f..93e01b90b4a21323c76293502110= 83a81eb549d4=20 > 100644 > --- a/arch/mips/kernel/smp-cps.c > +++ b/arch/mips/kernel/smp-cps.c > @@ -40,6 +40,7 @@ static u64 core_entry_reg; > static phys_addr_t cps_vec_pa; >=20 > struct cluster_boot_config *mips_cps_cluster_bootcfg; > +struct cpumask __cpu_primary_cluster_mask __read_mostly; >=20 > static void power_up_other_cluster(unsigned int cluster) > { > @@ -225,6 +226,7 @@ static void __init cps_smp_setup(void) > if (mips_cm_revision() >=3D CM_REV_CM3_5) > power_up_other_cluster(cl); >=20 > + cpumask_set_cpu(nvpes, &__cpu_primary_cluster_mask); > ncores =3D mips_cps_numcores(cl); > for (c =3D 0; c < ncores; c++) { > core_vpes =3D core_vpe_count(cl, c); > @@ -281,6 +283,24 @@ static void __init cps_smp_setup(void) > #endif /* CONFIG_MIPS_MT_FPAFF */ > } >=20 > +unsigned long calibrate_delay_is_known(void) > +{ > + int i, this_cpu =3D smp_processor_id(), primary_cpu_cluster =3D 0; > + > + /* The calibration has to be done on the primary CPU of the cluster = */ > + if (cpumask_test_cpu(this_cpu, &__cpu_primary_cluster_mask)) > + return 0; > + > + /* Look for the primary CPU of the cluster this CPU belongs to */ > + for_each_cpu(i, &__cpu_primary_cluster_mask) { > + /* we reach the next cluster */ > + if (i > this_cpu) > + break; > + primary_cpu_cluster =3D i; > + } > + return cpu_data[primary_cpu_cluster].udelay_val; > +} > + > static void __init cps_prepare_cpus(unsigned int max_cpus) > { > unsigned int nclusters, ncores, core_vpes, c, cl, cca; > > --- > base-commit: 3b3704261e851e25983860e4c352f1f73786f4ab > change-id: 20250520-smp_calib-6d3009e1f5b9 > > Best regards, > --=20 > Gr=C3=A9gory CLEMENT, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com --=20 - Jiaxun