From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751214AbcGMEFG (ORCPT ); Wed, 13 Jul 2016 00:05:06 -0400 Received: from regular1.263xmail.com ([211.150.99.139]:48830 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750916AbcGMEFA (ORCPT ); Wed, 13 Jul 2016 00:05:00 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: william.wu@rock-chips.com X-FST-TO: devicetree@vger.kernel.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: william.wu@rock-chips.com X-UNIQUE-TAG: <9184605c4ef2f113ea3c3a8ea600eb89> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH v6 3/5] usb: dwc3: add phyif_utmi_quirk To: Rob Herring References: <1467860066-15142-1-git-send-email-william.wu@rock-chips.com> <1467860066-15142-4-git-send-email-william.wu@rock-chips.com> <20160711145854.GB16636@rob-hp-laptop> Cc: gregkh@linuxfoundation.org, balbi@kernel.org, heiko@sntech.de, linux-rockchip@lists.infradead.org, briannorris@google.com, dianders@google.com, kever.yang@rock-chips.com, huangtao@rock-chips.com, frank.wang@rock-chips.com, eddie.cai@rock-chips.com, John.Youn@synopsys.com, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, sergei.shtylyov@cogentembedded.com, mark.rutland@arm.com, devicetree@vger.kernel.org From: "William.wu" Message-ID: <8c62e88e-aa13-a978-1b92-2fe942671c04@rock-chips.com> Date: Wed, 13 Jul 2016 12:02:29 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: <20160711145854.GB16636@rob-hp-laptop> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Dear Rob, On 2016/7/11 22:58, Rob Herring wrote: > On Thu, Jul 07, 2016 at 10:54:24AM +0800, William Wu wrote: >> Add a quirk to configure the core to support the >> UTMI+ PHY with an 8- or 16-bit interface. UTMI+ PHY >> interface is hardware property, and it's platform >> dependent. Normall, the PHYIf can be configured > s/Normall/Normally/ Yeah，I'll fix it.:-) > s/PHYIf/PHYIF/ Refer to DWC3 controller databook, "PHY Interface" called "PHYIf", so I describe "PHYIf" here. However， "PHYIF”seems more the norm, I'll fix it.:-) > >> during coreconsultant. But for some specific usb > s/usb/USB/ Thanks, I'll fix it.:-) > >> cores(e.g. rk3399 soc dwc3), the default PHYIf >> configuration value is fault, so we need to >> reconfigure it by software. >> >> And refer to the dwc3 databook, the GUSB2PHYCFG.USBTRDTIM > s/dwc3/DWC3/ Thanks, I'll fix it too. > >> must be set to the corresponding value according to >> the UTMI+ PHY interface. > And wrap your lines at 70-74 characters. Thanks for your suggestion, I'll pay attention to this problem next patch.:-) Best Regards， William Wu > > Rob > > >