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Tue, 04 Nov 2025 08:51:21 -0800 (PST) X-Google-Smtp-Source: AGHT+IGaLO6FN0FgIEDIwpqrjcy5p2PW1tPvFsUVt6Qr/tHg7dp6PNqNViYh5WVOVGls3SLKLHAw1w== X-Received: by 2002:a05:6a20:7286:b0:2ff:3752:8388 with SMTP id adf61e73a8af0-348cbda9840mr22905967637.32.1762275080450; Tue, 04 Nov 2025 08:51:20 -0800 (PST) Received: from [192.168.29.63] ([49.43.227.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3415a1c3c6asm5091872a91.8.2025.11.04.08.51.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 04 Nov 2025 08:51:20 -0800 (PST) Message-ID: <8c664765-2c5a-4e42-8390-5969f0bce671@oss.qualcomm.com> Date: Tue, 4 Nov 2025 22:21:13 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] PCI: qcom: Program correct T_POWER_ON value for L1.2 exit timing To: Konrad Dybcio , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com, quic_vbadigan@quicinc.com References: <20251104-t_power_on_fux-v1-1-eb5916e47fd7@oss.qualcomm.com> <29b32098-39ca-440d-9b51-915157b752b5@oss.qualcomm.com> <2d4a192f-45b2-4aee-bcc9-dbe0dce0aa93@oss.qualcomm.com> <571d5733-be1b-449c-ba5a-414e0f950463@oss.qualcomm.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <571d5733-be1b-449c-ba5a-414e0f950463@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=dNyrWeZb c=1 sm=1 tr=0 ts=690a2f0a cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ISmZZG41GQzdpg15mxjwIw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Kzw4ZGRcYsZX5uRzB6oA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-GUID: oEFQA3xV_ELSo3NyIUPkA5dSzpG_SD1N X-Proofpoint-ORIG-GUID: oEFQA3xV_ELSo3NyIUPkA5dSzpG_SD1N X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTA0MDE0MCBTYWx0ZWRfX+OLvQfrW5bZP L+Z/dK+ydbghILm5IaM/XP8bxHFuMwgWVZF5e997i8E2iuxEQCR741841QCGyAUQpwHpEz8sjUw PO3u5YSLUaa0Si8BkdYXuyOvyTbou9hJfIY/OYyTgxN1csyis56+SGl9VpH35HzG+Bsam2lfqIR GPO0OwSf+G8/Ku/rMdsMFoZjnvCGXgRZahTSQd37BDRBusm3+QZV5FBoRDVftdhEj962tzLkj0W TF9rzwa5XqVG/Fu09mnQy8BiVlr6jKLMLydx+7BGnyvyQzny/Au2TjtwP6jok1ObF9MDtjx3Et7 VW6bWaxiZpAN1Z7SvpYGj8tZxiPYt12+thSsZ4YG5Crw4koBJaJ95ZOTzHXwZKQckAtMVWTLFkM posnNxYUak4uKVju8zVEaFxrQ3RCaw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-04_02,2025-11-03_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 adultscore=0 priorityscore=1501 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511040140 On 11/4/2025 10:13 PM, Konrad Dybcio wrote: > On 11/4/25 5:38 PM, Krishna Chaitanya Chundru wrote: >> On 11/4/2025 5:59 PM, Konrad Dybcio wrote: >>> On 11/4/25 1:12 PM, Krishna Chaitanya Chundru wrote: >>>> The T_POWER_ON indicates the time (in μs) that a Port requires the port >>>> on the opposite side of Link to wait in L1.2.Exit after sampling CLKREQ# >>>> asserted before actively driving the interface. This value is used by >>>> the ASPM driver to compute the LTR_L1.2_THRESHOLD. >>>> >>>> Currently, the root port exposes a T_POWER_ON value of zero in the L1SS >>>> capability registers, leading to incorrect LTR_L1.2_THRESHOLD calculations. >>>> This can result in improper L1.2 exit behavior and can trigger AER's. >>>> >>>> To address this, program the T_POWER_ON value to 80us (scale = 1, >>>> value = 8) in the PCI_L1SS_CAP register during host initialization. This >>>> ensures that ASPM can take the root port's T_POWER_ON value into account >>>> while calculating the LTR_L1.2_THRESHOLD value. >>> Is 80us a meaningful value, or "just happens to work"? >> This value is given by hardware team. > Sorry I asked the wrong question > > Is it something that comes from the spec (PCI or DWC), or is it qc > specific? T power ON value is part of the PCIe spec, expectation is this value needs to be set in the hardware only, In QC this value is Zero so it requires sw support to program this correctly before enumeration. - Krishna Chaitanya. > Konrad